From: Adhemerval Zanella via Libc-alpha <libc-alpha@sourceware.org>
To: libc-alpha@sourceware.org, Vincent Chen <vincent.chen@sifive.com>,
palmer@dabbelt.com
Cc: andrew@sifive.com
Subject: Re: [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch
Date: Fri, 1 Oct 2021 10:04:01 -0300 [thread overview]
Message-ID: <b37235c2-7390-61a1-37a8-ab0771754e6f@linaro.org> (raw)
In-Reply-To: <1631497278-29829-4-git-send-email-vincent.chen@sifive.com>
On 12/09/2021 22:41, Vincent Chen wrote:
> According to the RISC-V V extension specification, all vector registers
> except VCSR are caller-saved registers. The VCSR (vxrm + vxsat) has thread
> storage duration. Therefore, only VCSR needs to be added to the user
> context operation.
> ---
> sysdeps/riscv/Makefile | 5 ++++
> sysdeps/riscv/rtld-global-offsets.sym | 7 +++++
> sysdeps/unix/sysv/linux/riscv/bits/hwcap.h | 31 +++++++++++++++++++++
> sysdeps/unix/sysv/linux/riscv/getcontext.S | 22 ++++++++++++++-
> sysdeps/unix/sysv/linux/riscv/setcontext.S | 22 +++++++++++++++
> sysdeps/unix/sysv/linux/riscv/swapcontext.S | 41 ++++++++++++++++++++++++++++
> sysdeps/unix/sysv/linux/riscv/sysdep.h | 1 +
> sysdeps/unix/sysv/linux/riscv/ucontext_i.sym | 6 ++++
> 8 files changed, 134 insertions(+), 1 deletion(-)
> create mode 100644 sysdeps/riscv/rtld-global-offsets.sym
> create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h
>
> diff --git a/sysdeps/riscv/Makefile b/sysdeps/riscv/Makefile
> index 20a9968..cda3ded 100644
> --- a/sysdeps/riscv/Makefile
> +++ b/sysdeps/riscv/Makefile
> @@ -2,6 +2,11 @@ ifeq ($(subdir),misc)
> sysdep_headers += sys/asm.h
> endif
>
> +ifeq ($(subdir),csu)
> +# get offset to rtld_global._dl_hwcap and rtld_global._dl_hwcap2.
> +gen-as-const-headers += rtld-global-offsets.sym
> +endif
> +
> # RISC-V's assembler also needs to know about PIC as it changes the definition
> # of some assembler macros.
> ASFLAGS-.os += $(pic-ccflag)
> diff --git a/sysdeps/riscv/rtld-global-offsets.sym b/sysdeps/riscv/rtld-global-offsets.sym
> new file mode 100644
> index 0000000..ff4e97f
> --- /dev/null
> +++ b/sysdeps/riscv/rtld-global-offsets.sym
> @@ -0,0 +1,7 @@
> +#define SHARED 1
> +
> +#include <ldsodefs.h>
> +
> +#define rtld_global_ro_offsetof(mem) offsetof (struct rtld_global_ro, mem)
> +
> +RTLD_GLOBAL_RO_DL_HWCAP_OFFSET rtld_global_ro_offsetof (_dl_hwcap)
> diff --git a/sysdeps/unix/sysv/linux/riscv/bits/hwcap.h b/sysdeps/unix/sysv/linux/riscv/bits/hwcap.h
> new file mode 100644
> index 0000000..e6c5ef5
> --- /dev/null
> +++ b/sysdeps/unix/sysv/linux/riscv/bits/hwcap.h
> @@ -0,0 +1,31 @@
> +/* Defines for bits in AT_HWCAP. RISC-V Linux version.
> + Copyright (C) 2021 Free Software Foundation, Inc.
> + This file is part of the GNU C Library.
> +
> + The GNU C Library is free software; you can redistribute it and/or
> + modify it under the terms of the GNU Lesser General Public
> + License as published by the Free Software Foundation; either
> + version 2.1 of the License, or (at your option) any later version.
> +
> + The GNU C Library is distributed in the hope that it will be useful,
> + but WITHOUT ANY WARRANTY; without even the implied warranty of
> + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + Lesser General Public License for more details.
> +
> + You should have received a copy of the GNU Lesser General Public
> + License along with the GNU C Library; if not, see
> + <http://www.gnu.org/licenses/>. */
> +
> +#if !defined (_SYS_AUXV_H) && !defined (_LINUX_RISCV_SYSDEP_H)
_LINUX_RISCV_SYSDEP_H is defined by an internal header only, so I
think it should no be referenced by an exported one.
> +# error "Never include <bits/hwcap.h> directly; use <sys/auxv.h> instead."
> +#endif
> +
> +/* The following must match the kernel's <asm/hwcap.h>. */
> +#define HWCAP_ISA_I 0x100 //(1 << ('I' - 'A'))
> +#define HWCAP_ISA_M 0x1000 //(1 << ('M' - 'A'))
> +#define HWCAP_ISA_A 0x1 //(1 << ('A' - 'A'))
> +#define HWCAP_ISA_F 0x20 //(1 << ('F' - 'A'))
> +#define HWCAP_ISA_D 0x8 //(1 << ('D' - 'A'))
> +#define HWCAP_ISA_C 0x4 //(1 << ('C' - 'A'))
> +#define HWCAP_ISA_V 0x200000 //(1 << ('V' - 'A'))
> +
> diff --git a/sysdeps/unix/sysv/linux/riscv/getcontext.S b/sysdeps/unix/sysv/linux/riscv/getcontext.S
> index d6a9bbc..840d8fe 100644
> --- a/sysdeps/unix/sysv/linux/riscv/getcontext.S
> +++ b/sysdeps/unix/sysv/linux/riscv/getcontext.S
> @@ -16,6 +16,8 @@
> License along with the GNU C Library. If not, see
> <https://www.gnu.org/licenses/>. */
>
> +#include <sysdep.h>
> +#include <rtld-global-offsets.h>
> #include "ucontext-macros.h"
>
> /* int getcontext (ucontext_t *ucp) */
> @@ -39,6 +41,25 @@ LEAF (__getcontext)
> SAVE_INT_REG (s10, 26, a0)
> SAVE_INT_REG (s11, 27, a0)
>
> +#ifdef __riscv_vector
I take '__riscv_vector' would be defined by the compiler (although there is
no gcc support yet). Why do you need to build iff vector extension is being
use if you are checking the hwcap?
For __riscv_float_abi_soft it does make sense since 'frsr' will be issue
regardless.
> +# ifdef SHARED
> + la t1, _rtld_global_ro
> + REG_L t1, RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(t1)
> +# else
> + la t1, _dl_hwcap
> + REG_L t1, (t1)
> +# endif
> + li t2, HWCAP_ISA_V
> + and t2, t1, t2
> + beqz t2, 1f
> + addi t2, a0, MCONTEXT_EXTENSION
> + li t1, RVV_MAGIC
> + sw t1, (t2)
> + csrr t1, vcsr
> + REG_S t1, VCSR_OFFSET(t2)
> +1:
> +#endif
> +
> #ifndef __riscv_float_abi_soft
> frsr a1
>
> @@ -73,5 +94,4 @@ LEAF (__getcontext)
> 99: j __syscall_error
>
> PSEUDO_END (__getcontext)
> -
> weak_alias (__getcontext, getcontext)
> diff --git a/sysdeps/unix/sysv/linux/riscv/setcontext.S b/sysdeps/unix/sysv/linux/riscv/setcontext.S
> index 9510518..d2404fb 100644
> --- a/sysdeps/unix/sysv/linux/riscv/setcontext.S
> +++ b/sysdeps/unix/sysv/linux/riscv/setcontext.S
> @@ -16,6 +16,8 @@
> License along with the GNU C Library. If not, see
> <https://www.gnu.org/licenses/>. */
>
> +#include <sysdep.h>
> +#include <rtld-global-offsets.h>
> #include "ucontext-macros.h"
>
> /* int __setcontext (const ucontext_t *ucp)
> @@ -64,6 +66,26 @@ LEAF (__setcontext)
> fssr t1
> #endif /* __riscv_float_abi_soft */
>
> +#ifdef __riscv_vector
> +#ifdef SHARED
> + la t1, _rtld_global_ro
> + REG_L t1, RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(t1)
> +#else
> + la t1, _dl_hwcap
> + REG_L t1, (t1)
> +#endif
> + li t2, HWCAP_ISA_V
> + and t2, t1, t2
> + beqz t2, 1f
> + li t1, RVV_MAGIC
> + addi t2, t0, MCONTEXT_EXTENSION
> + lw a1, (t2)
> + bne a1, t1, 1f
> + REG_L t1, VCSR_OFFSET(t2)
> + csrw vcsr, t1
> +1:
> +#endif
> +
> /* Note the contents of argument registers will be random
> unless makecontext() has been called. */
> RESTORE_INT_REG (t1, 0, t0)
> diff --git a/sysdeps/unix/sysv/linux/riscv/swapcontext.S b/sysdeps/unix/sysv/linux/riscv/swapcontext.S
> index df0f699..94ae8e4 100644
> --- a/sysdeps/unix/sysv/linux/riscv/swapcontext.S
> +++ b/sysdeps/unix/sysv/linux/riscv/swapcontext.S
> @@ -16,6 +16,8 @@
> License along with the GNU C Library. If not, see
> <https://www.gnu.org/licenses/>. */
>
> +#include <sysdep.h>
> +#include <rtld-global-offsets.h>
> #include "ucontext-macros.h"
>
> /* int swapcontext (ucontext_t *oucp, const ucontext_t *ucp) */
> @@ -40,6 +42,25 @@ LEAF (__swapcontext)
> SAVE_INT_REG (s10, 26, a0)
> SAVE_INT_REG (s11, 27, a0)
>
> +#ifdef __riscv_vector
> +#ifdef SHARED
> + la t1, _rtld_global_ro
> + REG_L t1, RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(t1)
> +#else
> + la t1, _dl_hwcap
> + REG_L t1, (t1)
> +#endif
> + li t2, HWCAP_ISA_V
> + and t2, t1, t2
> + beqz t2, 1f
> + addi t2, a0, MCONTEXT_EXTENSION
> + li t1, RVV_MAGIC
> + sw t1, (t2)
> + csrr t1, vcsr
> + REG_S t1, VCSR_OFFSET(t2)
> +1:
> +#endif
> +
> #ifndef __riscv_float_abi_soft
> frsr a1
>
> @@ -89,6 +110,26 @@ LEAF (__swapcontext)
> fssr t1
> #endif /* __riscv_float_abi_soft */
>
> +#ifdef __riscv_vector
> +#ifdef SHARED
> + la t1, _rtld_global_ro
> + REG_L t1, RTLD_GLOBAL_RO_DL_HWCAP_OFFSET(t1)
> +#else
> + la t1, _dl_hwcap
> + REG_L t1, (t1)
> +#endif
> + li t2, HWCAP_ISA_V
> + and t2, t1, t2
> + beqz t2, 1f
> + li t1, RVV_MAGIC
> + addi t2, t0, MCONTEXT_EXTENSION
> + lw a1, (t2)
> + bne a1, t1, 1f
> + REG_L t1, VCSR_OFFSET(t2)
> + csrw vcsr, t1
> +1:
> +#endif
> +
> /* Note the contents of argument registers will be random
> unless makecontext() has been called. */
> RESTORE_INT_REG (t1, 0, t0)
> diff --git a/sysdeps/unix/sysv/linux/riscv/sysdep.h b/sysdeps/unix/sysv/linux/riscv/sysdep.h
> index 37ff07a..c9f8fd8 100644
> --- a/sysdeps/unix/sysv/linux/riscv/sysdep.h
> +++ b/sysdeps/unix/sysv/linux/riscv/sysdep.h
> @@ -50,6 +50,7 @@
>
> #ifdef __ASSEMBLER__
>
> +# include <bits/hwcap.h>
> # include <sys/asm.h>
>
> # define ENTRY(name) LEAF(name)
> diff --git a/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym b/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
> index be55b26..4037473 100644
> --- a/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
> +++ b/sysdeps/unix/sysv/linux/riscv/ucontext_i.sym
> @@ -2,6 +2,7 @@
> #include <signal.h>
> #include <stddef.h>
> #include <sys/ucontext.h>
> +#include <asm/sigcontext.h>
>
> -- Constants used by the rt_sigprocmask call.
>
> @@ -27,5 +28,10 @@ STACK_FLAGS stack (ss_flags)
>
> MCONTEXT_GREGS mcontext (__gregs)
> MCONTEXT_FPREGS mcontext (__fpregs)
> +MCONTEXT_EXTENSION mcontext (__reserved)
>
> UCONTEXT_SIZE sizeof (ucontext_t)
> +
> +VCSR_OFFSET offsetof (struct __riscv_v_state, vcsr)
> +
> +RVV_MAGIC
>
next prev parent reply other threads:[~2021-10-01 13:04 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 1:41 [RFC patch 0/5] RISC-V: Add vector ISA support Vincent Chen
2021-09-13 1:41 ` [RFC patch 1/5] RISC-V: Remove riscv-specific sigcontext.h Vincent Chen
2021-09-13 1:41 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Vincent Chen
2021-09-13 13:44 ` Florian Weimer via Libc-alpha
2021-09-13 13:52 ` Rich Felker
2021-09-16 8:02 ` Vincent Chen
2021-09-16 8:14 ` Florian Weimer via Libc-alpha
2021-09-18 3:04 ` Vincent Chen
2022-12-09 3:39 ` RISCV kernel struct sigcontext expansion for V regs and potential glibc ABI break (was Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.) Vineet Gupta
2022-12-09 4:03 ` Vineet Gupta
2022-12-20 20:05 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Vineet Gupta
2022-12-21 15:53 ` Vincent Chen
2022-12-21 19:45 ` Vineet Gupta
2022-12-21 19:52 ` Vineet Gupta
2022-12-22 3:37 ` Vincent Chen
2022-12-22 19:25 ` Vineet Gupta
2022-12-23 2:27 ` Vincent Chen
2022-12-23 19:42 ` Vineet Gupta
2022-12-22 5:32 ` Richard Henderson via Libc-alpha
2022-12-22 18:33 ` Andy Chiu
2022-12-22 20:27 ` Vineet Gupta
2022-12-28 10:53 ` Andy Chiu
2023-01-03 19:17 ` Vineet Gupta
2023-01-04 16:34 ` Andy Chiu
2023-01-04 20:46 ` Vineet Gupta
2023-01-04 21:29 ` Philipp Tomsich
2023-01-04 21:37 ` Andrew Waterman
2023-01-04 22:43 ` Vineet Gupta
2023-01-09 13:33 ` Kito Cheng
2023-01-09 19:16 ` Vineet Gupta
2023-01-10 13:21 ` Kito Cheng
2023-01-10 18:07 ` Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) Vineet Gupta
2023-01-11 1:22 ` Richard Henderson via Libc-alpha
2023-01-11 4:28 ` Jeff Law
2023-01-11 4:57 ` Richard Henderson via Libc-alpha
2023-01-11 5:07 ` Jeff Law
2023-01-11 6:00 ` Andy Chiu
2023-01-11 6:20 ` Jeff Law
2023-01-11 9:28 ` Andy Chiu
2023-01-11 12:13 ` Andy Chiu
2023-01-23 12:17 ` Conor Dooley via Libc-alpha
2023-01-23 13:29 ` Andy Chiu
2023-01-11 5:05 ` Anup Patel
2023-01-11 5:23 ` Richard Henderson via Libc-alpha
2022-12-22 22:33 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Richard Henderson via Libc-alpha
2022-12-22 23:47 ` Conor Dooley via Libc-alpha
2022-12-22 23:58 ` Vineet Gupta
2022-12-22 20:30 ` Vineet Gupta
2022-12-22 21:38 ` Andrew Waterman
2022-12-22 1:50 ` Vincent Chen
2022-12-22 5:34 ` Richard Henderson via Libc-alpha
2021-09-16 23:56 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Ben Woodard via Libc-alpha
2021-09-18 3:15 ` Vincent Chen
2021-09-20 16:41 ` DJ Delorie via Libc-alpha
2021-09-20 17:10 ` Florian Weimer via Libc-alpha
2021-10-01 1:43 ` Vincent Chen
2021-10-01 12:08 ` Adhemerval Zanella via Libc-alpha
2021-09-17 17:03 ` Rich Felker
2021-09-18 3:19 ` Vincent Chen
2021-09-13 1:41 ` [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch Vincent Chen
2021-09-14 23:48 ` Joseph Myers
2021-09-15 0:13 ` Andrew Waterman
2021-09-16 9:20 ` Vincent Chen
2021-10-01 13:04 ` Adhemerval Zanella via Libc-alpha [this message]
2021-09-13 1:41 ` [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers Vincent Chen
2021-09-13 13:51 ` Rich Felker
2021-09-16 9:25 ` Vincent Chen
2021-09-13 1:41 ` [RFC 5/5] RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment Vincent Chen
2021-09-14 23:43 ` Joseph Myers
2021-09-15 10:42 ` Florian Weimer via Libc-alpha
2021-09-15 14:31 ` H.J. Lu via Libc-alpha
2021-09-16 10:21 ` Vincent Chen
2021-09-13 19:11 ` [RFC patch 0/5] RISC-V: Add vector ISA support Vineet Gupta via Libc-alpha
2021-09-15 19:37 ` Jim Wilson
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:30 ` Andrew Waterman
2021-11-09 22:03 ` Darius Rad
2021-11-09 22:18 ` Andrew Waterman
2021-11-10 11:39 ` Darius Rad
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