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From: Kito Cheng <kito.cheng@sifive.com>
To: Vineet Gupta <vineetg@rivosinc.com>
Cc: "Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Andy Chiu" <andy.chiu@sifive.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Vincent Chen" <vincent.chen@sifive.com>,
	"Florian Weimer" <fweimer@redhat.com>,
	"Rich Felker" <dalias@libc.org>,
	"Andrew Waterman" <andrew@sifive.com>,
	"Palmer Dabbelt" <palmer@rivosinc.com>,
	"Christoph Müllner" <christoph.muellner@vrull.eu>,
	davidlt@rivosinc.com, "Arnd Bergmann" <arnd@arndb.de>,
	"Björn Töpel" <bjorn@kernel.org>,
	"Szabolcs Nagy" <szabolcs.nagy@arm.com>,
	"Greentime Hu" <greentime.hu@sifive.com>,
	"Aaron Durbin" <adurbin@rivosinc.com>,
	"Andrew de los Reyes" <adlr@rivosinc.com>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"GNU C Library" <libc-alpha@sourceware.org>
Subject: Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break
Date: Mon, 9 Jan 2023 21:33:20 +0800	[thread overview]
Message-ID: <CALLt3ThickhyW5gX6LNjHXza484Xb5Cg8t7OUYH6hoA3V3GpAg@mail.gmail.com> (raw)
In-Reply-To: <1f8f1d21-4a19-54fe-8b29-bf9e2a8501d7@rivosinc.com>

Hi Vineet:

> >>>> The new Kconfig CONFIG_RISCV_VSTATE_INIT_ALL seems like a
> >>>> hack bolted on top.
> >>> IIUC, most opinions suggested that we should keep the default Vector
> >>> state to ON in thread:
> >>> https://lore.kernel.org/all/20220921214439.1491510-17-stillson@rivosinc.com/T/#u
> >> Actually community feedback is that they *don't * want the default
> >> vector state to be on due to power implications, increased stack and
> >> memory usage for vector contents (in that thread and else where as
> >> well). So we should keep it disabled by default, but indeed we could
> >> have that Kconfig option to enable it. Granted distro kernels will keep
> >> it disabled by default, this lets vendors enable it selectively until
> >> the full userspace enabling bits are in place.
> > Should we punt this to the ELF (e.g., using a RISC-V specific
> > attribute) and take a per-process decision on whether to start in ON
> > or OFF?
> > I don't feel fully comfortable with a KCONFIG that could change and
> > invalidate the assumptions a userspace process could have made…
>
> The Kconfig is just a stop gap for vendors to enable V development while
> the full userspace stuff is sorted out.
>
> Indeed RISCV_ATTRIBUTES section has -march info, but we need to do some
> development around it to parse it and use it.

I don't think RISCV_ATTRIBUTES is the right place to check that - even if the
program compiles without V, it still can enable V and then get performance
benefit by ifunc in glibc, or even some 3rd party libraries might also be
optimized with V ext.

And don't forget other shared libraries in the system,
are we going to check all dependent libraries at program load time?
it will require resolving the library dependency at kernel.
Or we intend to enable V only if executable compiles with V?

> There are still corner cases such as non-V executable dlopen a dso - so
> kernel elf parser doing this might not cover all cases.
>
> Similar logic will need to be added to glibc loader - eventually.
>
> Adding the full plumbing is a chicken-and-egg problem.
>
>
> > Alternatively, we could establish the convention of having two stub
> > libraries that set up either enabled or disable state from their
> > .init_array to provide a mechanism for folks that want to make an
> > explicit assumption.  Although this may try to overdesign a solution
> > for a non-issue.
>
> I was thinking more along the lines of x86 GLIBC_TUNABLES to enable it
> via env/sub-shell on a per-task basis - the tunable hook could in turn
> verify that Vector support does exist - or it could invoke the prctl
> unconditionally (which would fail if V didn't exist etc).

  reply	other threads:[~2023-01-09 13:33 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-13  1:41 [RFC patch 0/5] RISC-V: Add vector ISA support Vincent Chen
2021-09-13  1:41 ` [RFC patch 1/5] RISC-V: Remove riscv-specific sigcontext.h Vincent Chen
2021-09-13  1:41 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Vincent Chen
2021-09-13 13:44   ` Florian Weimer via Libc-alpha
2021-09-13 13:52     ` Rich Felker
2021-09-16  8:02       ` Vincent Chen
2021-09-16  8:14         ` Florian Weimer via Libc-alpha
2021-09-18  3:04           ` Vincent Chen
2022-12-09  3:39             ` RISCV kernel struct sigcontext expansion for V regs and potential glibc ABI break (was Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.) Vineet Gupta
2022-12-09  4:03               ` Vineet Gupta
2022-12-20 20:05               ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Vineet Gupta
2022-12-21 15:53                 ` Vincent Chen
2022-12-21 19:45                   ` Vineet Gupta
2022-12-21 19:52                     ` Vineet Gupta
2022-12-22  3:37                       ` Vincent Chen
2022-12-22 19:25                         ` Vineet Gupta
2022-12-23  2:27                           ` Vincent Chen
2022-12-23 19:42                             ` Vineet Gupta
2022-12-22  5:32                       ` Richard Henderson via Libc-alpha
2022-12-22 18:33                         ` Andy Chiu
2022-12-22 20:27                           ` Vineet Gupta
2022-12-28 10:53                             ` Andy Chiu
2023-01-03 19:17                               ` Vineet Gupta
2023-01-04 16:34                                 ` Andy Chiu
2023-01-04 20:46                                   ` Vineet Gupta
2023-01-04 21:29                                     ` Philipp Tomsich
2023-01-04 21:37                                       ` Andrew Waterman
2023-01-04 22:43                                       ` Vineet Gupta
2023-01-09 13:33                                         ` Kito Cheng [this message]
2023-01-09 19:16                                           ` Vineet Gupta
2023-01-10 13:21                                             ` Kito Cheng
2023-01-10 18:07                                               ` Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) Vineet Gupta
2023-01-11  1:22                                                 ` Richard Henderson via Libc-alpha
2023-01-11  4:28                                                   ` Jeff Law
2023-01-11  4:57                                                     ` Richard Henderson via Libc-alpha
2023-01-11  5:07                                                       ` Jeff Law
2023-01-11  6:00                                                         ` Andy Chiu
2023-01-11  6:20                                                           ` Jeff Law
2023-01-11  9:28                                                             ` Andy Chiu
2023-01-11 12:13                                                               ` Andy Chiu
2023-01-23 12:17                                                                 ` Conor Dooley via Libc-alpha
2023-01-23 13:29                                                                   ` Andy Chiu
2023-01-11  5:05                                                   ` Anup Patel
2023-01-11  5:23                                                   ` Richard Henderson via Libc-alpha
2022-12-22 22:33                           ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Richard Henderson via Libc-alpha
2022-12-22 23:47                           ` Conor Dooley via Libc-alpha
2022-12-22 23:58                             ` Vineet Gupta
2022-12-22 20:30                         ` Vineet Gupta
2022-12-22 21:38                           ` Andrew Waterman
2022-12-22  1:50                     ` Vincent Chen
2022-12-22  5:34                     ` Richard Henderson via Libc-alpha
2021-09-16 23:56         ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Ben Woodard via Libc-alpha
2021-09-18  3:15           ` Vincent Chen
2021-09-20 16:41             ` DJ Delorie via Libc-alpha
2021-09-20 17:10               ` Florian Weimer via Libc-alpha
2021-10-01  1:43                 ` Vincent Chen
2021-10-01 12:08                   ` Adhemerval Zanella via Libc-alpha
2021-09-17 17:03         ` Rich Felker
2021-09-18  3:19           ` Vincent Chen
2021-09-13  1:41 ` [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch Vincent Chen
2021-09-14 23:48   ` Joseph Myers
2021-09-15  0:13     ` Andrew Waterman
2021-09-16  9:20       ` Vincent Chen
2021-10-01 13:04   ` Adhemerval Zanella via Libc-alpha
2021-09-13  1:41 ` [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers Vincent Chen
2021-09-13 13:51   ` Rich Felker
2021-09-16  9:25     ` Vincent Chen
2021-09-13  1:41 ` [RFC 5/5] RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment Vincent Chen
2021-09-14 23:43   ` Joseph Myers
2021-09-15 10:42     ` Florian Weimer via Libc-alpha
2021-09-15 14:31       ` H.J. Lu via Libc-alpha
2021-09-16 10:21         ` Vincent Chen
2021-09-13 19:11 ` [RFC patch 0/5] RISC-V: Add vector ISA support Vineet Gupta via Libc-alpha
2021-09-15 19:37   ` Jim Wilson
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:30   ` Andrew Waterman
2021-11-09 22:03     ` Darius Rad
2021-11-09 22:18       ` Andrew Waterman
2021-11-10 11:39         ` Darius Rad

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