[RFC patch 0/5] RISC-V: Add vector ISA support

[Vincent Chen <vincent.chen@sifive.com>]

This patchset adds required ports to support RISC-V Vector (RVV) extension.

Since the length of the vector register in RVV (the theoretical maximum
is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back
up all vector registers in the signal context. This patchset expands the
default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack
size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also
places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the
auxiliary vector to inform user, so user still can know the sutible minimum
signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater
than 128 bytes. 

In addition, according to the specification, the VCSR that combines VXRM and
VXSAT has thread storage duration, so this patchset adds the required user
context operation for it.

Finally, the RISC-V glibc customized sigcontext.h has been removed in this
patchset. to reduce the synchronization work when new extension support is
introduced to the Linux environment. However, it may bring some backward
incompatible issues. Therefore, I sent an RFC patch
(https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html)
to discuss this modification before this patchset. As I mentioned in the
RFC patch thread, I used OpenEmbeded to evaluate the impact. During the
tests, I didn't get any compiler errors. Therefore, I infer that this
modification may not cause server backward incompatible issues at this
moment.

1. The RISC-V V-extension draft v1.0 can be found in
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
2. The associated kernel implementation can be found in
http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html
3. QEMU with RISC-V V-extension support can be found in
https://github.com/sifive/qemu/tree/rvv-1.0

Vincent Chen (5):
  RISC-V: Remove riscv-specific sigcontext.h
  RISC-V: Reserve about 5K space in mcontext_t to support future ISA
    expansion.
  RISC-V: Save and restore VCSR when doing user context switch
  RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers
  RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment

 sysdeps/riscv/Makefile                             |  5 +++
 sysdeps/riscv/rtld-global-offsets.sym              |  7 ++++
 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h         | 31 ++++++++++++++++
 .../unix/sysv/linux/riscv/bits/pthread_stack_min.h | 21 +++++++++++
 sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h    | 31 ----------------
 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h      | 32 +++++++++++++++++
 sysdeps/unix/sysv/linux/riscv/getcontext.S         | 22 +++++++++++-
 sysdeps/unix/sysv/linux/riscv/setcontext.S         | 22 ++++++++++++
 sysdeps/unix/sysv/linux/riscv/swapcontext.S        | 41 ++++++++++++++++++++++
 sysdeps/unix/sysv/linux/riscv/sys/ucontext.h       |  2 ++
 .../sysv/linux/riscv/sysconf-pthread_stack_min.h   | 39 ++++++++++++++++++++
 sysdeps/unix/sysv/linux/riscv/sysdep.h             |  1 +
 sysdeps/unix/sysv/linux/riscv/ucontext_i.sym       |  6 ++++
 13 files changed, 228 insertions(+), 32 deletions(-)
 create mode 100644 sysdeps/riscv/rtld-global-offsets.sym
 create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h
 create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/pthread_stack_min.h
 delete mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h
 create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h
 create mode 100644 sysdeps/unix/sysv/linux/riscv/sysconf-pthread_stack_min.h

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2.7.4