From: Andy Chiu <andy.chiu@sifive.com>
To: Jeff Law <jlaw@ventanamicro.com>
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Vineet Gupta" <vineetg@rivosinc.com>,
"Kito Cheng" <kito.cheng@sifive.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Vincent Chen" <vincent.chen@sifive.com>,
"Florian Weimer" <fweimer@redhat.com>,
"Rich Felker" <dalias@libc.org>,
"Andrew Waterman" <andrew@sifive.com>,
"Palmer Dabbelt" <palmer@rivosinc.com>,
"Christoph Müllner" <christoph.muellner@vrull.eu>,
davidlt@rivosinc.com, "Arnd Bergmann" <arnd@arndb.de>,
"Björn Töpel" <bjorn@kernel.org>,
"Szabolcs Nagy" <szabolcs.nagy@arm.com>,
"Greentime Hu" <greentime.hu@sifive.com>,
"Aaron Durbin" <adurbin@rivosinc.com>,
"Andrew de los Reyes" <adlr@rivosinc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"GNU C Library" <libc-alpha@sourceware.org>
Subject: Re: Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break)
Date: Wed, 11 Jan 2023 20:13:27 +0800 [thread overview]
Message-ID: <CABgGipVE3RnrNy1=8nsXUvW0w4XopHQuAzufQ66z6OWvU7wbwA@mail.gmail.com> (raw)
In-Reply-To: <CABgGipUCoykzeS5B1wSQxcxumCweRi2RDTKdD8u6ON63DV3EnQ@mail.gmail.com>
On Wed, Jan 11, 2023 at 5:28 PM Andy Chiu <andy.chiu@sifive.com> wrote:
>
> On Wed, Jan 11, 2023 at 2:20 PM Jeff Law <jlaw@ventanamicro.com> wrote:
> > Fault on first use is well understood and has been implemented on many
> > architectures through the decades, even with its warts.
>
> Unfortunately, we don't have a direct way of acknowledging if an
> illegal instruction is caused by illegitimate use of V instructions.
> Unlike ARM64, where reading ESR_EL1.EC is enough to distinguish the
> fault, we may have to perform a sw decode on the faulting instruction.
> Then see if it is the first-use fault, or a more general illegal
> instruction fault.
After taking more considerations, I think this could be minor. The
first V-instruction of a valid program that uses Vector is limited to
vset{i}vl{i}, vl<nf>r, or vs<nf>r. And perhaps some r/w of
vector-specific CSRs. Decoding these instructions should be relatively
constraint and easy. And we need this decoding only once for each
process since we don't have to do lazy save/restore.
>
> Yes, we may just enable V for a process whenever we find an OP-V major
> opcode, or a LOAD/STORE-FP with vector-encoded width on illegal
> instruction. But it could be kind of messy, IF, later extensions would
> also like to be enabled at first-use-fault. (e.g. ARM has SME followed
> by SVE). And implementing this decoding logic in sw just seems
> redundant to me because hw has already done that for us.
Let's limit our discussion to the scope of VS enablement for now.
>
> Besides, ARM64 has individual mappings of traps for the use of
> FP-related units in EL1 and EL0. So SIMD running in kernel mode would
> not take additional instruction to enable the unit. I assume these
> kinds of CSR-controlling instructions would have to flush hw internal
> buffers to some extent. And doing these takes additional latencies.
We already do some VS/FS settings on the entry of kernel code. So this
should be minor as well.
Anyway, I agree that faulting on first-uses is a better way to make
per-process control of VS feasible. Sorry for disturbing the list.
Thanks,
Andy
next prev parent reply other threads:[~2023-01-11 12:13 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 1:41 [RFC patch 0/5] RISC-V: Add vector ISA support Vincent Chen
2021-09-13 1:41 ` [RFC patch 1/5] RISC-V: Remove riscv-specific sigcontext.h Vincent Chen
2021-09-13 1:41 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Vincent Chen
2021-09-13 13:44 ` Florian Weimer via Libc-alpha
2021-09-13 13:52 ` Rich Felker
2021-09-16 8:02 ` Vincent Chen
2021-09-16 8:14 ` Florian Weimer via Libc-alpha
2021-09-18 3:04 ` Vincent Chen
2022-12-09 3:39 ` RISCV kernel struct sigcontext expansion for V regs and potential glibc ABI break (was Re: [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion.) Vineet Gupta
2022-12-09 4:03 ` Vineet Gupta
2022-12-20 20:05 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Vineet Gupta
2022-12-21 15:53 ` Vincent Chen
2022-12-21 19:45 ` Vineet Gupta
2022-12-21 19:52 ` Vineet Gupta
2022-12-22 3:37 ` Vincent Chen
2022-12-22 19:25 ` Vineet Gupta
2022-12-23 2:27 ` Vincent Chen
2022-12-23 19:42 ` Vineet Gupta
2022-12-22 5:32 ` Richard Henderson via Libc-alpha
2022-12-22 18:33 ` Andy Chiu
2022-12-22 20:27 ` Vineet Gupta
2022-12-28 10:53 ` Andy Chiu
2023-01-03 19:17 ` Vineet Gupta
2023-01-04 16:34 ` Andy Chiu
2023-01-04 20:46 ` Vineet Gupta
2023-01-04 21:29 ` Philipp Tomsich
2023-01-04 21:37 ` Andrew Waterman
2023-01-04 22:43 ` Vineet Gupta
2023-01-09 13:33 ` Kito Cheng
2023-01-09 19:16 ` Vineet Gupta
2023-01-10 13:21 ` Kito Cheng
2023-01-10 18:07 ` Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) Vineet Gupta
2023-01-11 1:22 ` Richard Henderson via Libc-alpha
2023-01-11 4:28 ` Jeff Law
2023-01-11 4:57 ` Richard Henderson via Libc-alpha
2023-01-11 5:07 ` Jeff Law
2023-01-11 6:00 ` Andy Chiu
2023-01-11 6:20 ` Jeff Law
2023-01-11 9:28 ` Andy Chiu
2023-01-11 12:13 ` Andy Chiu [this message]
2023-01-23 12:17 ` Conor Dooley via Libc-alpha
2023-01-23 13:29 ` Andy Chiu
2023-01-11 5:05 ` Anup Patel
2023-01-11 5:23 ` Richard Henderson via Libc-alpha
2022-12-22 22:33 ` Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break Richard Henderson via Libc-alpha
2022-12-22 23:47 ` Conor Dooley via Libc-alpha
2022-12-22 23:58 ` Vineet Gupta
2022-12-22 20:30 ` Vineet Gupta
2022-12-22 21:38 ` Andrew Waterman
2022-12-22 1:50 ` Vincent Chen
2022-12-22 5:34 ` Richard Henderson via Libc-alpha
2021-09-16 23:56 ` [RFC patch 2/5] RISC-V: Reserve about 5K space in mcontext_t to support future ISA expansion Ben Woodard via Libc-alpha
2021-09-18 3:15 ` Vincent Chen
2021-09-20 16:41 ` DJ Delorie via Libc-alpha
2021-09-20 17:10 ` Florian Weimer via Libc-alpha
2021-10-01 1:43 ` Vincent Chen
2021-10-01 12:08 ` Adhemerval Zanella via Libc-alpha
2021-09-17 17:03 ` Rich Felker
2021-09-18 3:19 ` Vincent Chen
2021-09-13 1:41 ` [RFC patch 3/5] RISC-V: Save and restore VCSR when doing user context switch Vincent Chen
2021-09-14 23:48 ` Joseph Myers
2021-09-15 0:13 ` Andrew Waterman
2021-09-16 9:20 ` Vincent Chen
2021-10-01 13:04 ` Adhemerval Zanella via Libc-alpha
2021-09-13 1:41 ` [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers Vincent Chen
2021-09-13 13:51 ` Rich Felker
2021-09-16 9:25 ` Vincent Chen
2021-09-13 1:41 ` [RFC 5/5] RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment Vincent Chen
2021-09-14 23:43 ` Joseph Myers
2021-09-15 10:42 ` Florian Weimer via Libc-alpha
2021-09-15 14:31 ` H.J. Lu via Libc-alpha
2021-09-16 10:21 ` Vincent Chen
2021-09-13 19:11 ` [RFC patch 0/5] RISC-V: Add vector ISA support Vineet Gupta via Libc-alpha
2021-09-15 19:37 ` Jim Wilson
2021-11-09 19:21 ` Darius Rad
2021-11-09 19:30 ` Andrew Waterman
2021-11-09 22:03 ` Darius Rad
2021-11-09 22:18 ` Andrew Waterman
2021-11-10 11:39 ` Darius Rad
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