From: "H.J. Lu via Libc-alpha" <libc-alpha@sourceware.org>
To: libc-alpha@sourceware.org
Subject: [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support
Date: Thu, 8 Oct 2020 09:12:32 -0700 [thread overview]
Message-ID: <20201008161232.135513-6-hjl.tools@gmail.com> (raw)
In-Reply-To: <20201008161232.135513-1-hjl.tools@gmail.com>
Add Fast Short REP CMP and SCA (FSRCS), Fast Short REP STO (FSRS) and
Fast Zero-Length REP MOV (FZLRM) support to <sys/platform/x86.h>.
---
manual/platform.texi | 9 +++++++++
sysdeps/x86/cpu-features.c | 3 +++
sysdeps/x86/sys/platform/x86.h | 9 +++++++++
sysdeps/x86/tst-get-cpu-features.c | 6 ++++++
4 files changed, 27 insertions(+)
diff --git a/manual/platform.texi b/manual/platform.texi
index 1e44525552..217a5c99ad 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -331,9 +331,18 @@ extensions.
@item
@code{FSGSBASE} -- RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE instructions.
+@item
+@code{FSRCS} -- Fast Short REP CMP and SCA.
+
@item
@code{FSRM} -- Fast Short REP MOV.
+@item
+@code{FSRS} -- Fast Short REP STO.
+
+@item
+@code{FZLRM} -- Fast Zero-Length REP MOV.
+
@item
@code{FXSR} -- FXSAVE and FXRSTOR instructions.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index b0fac22c27..286ff96771 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -93,6 +93,9 @@ update_usable (struct cpu_features *cpu_features)
CPU_FEATURE_SET_USABLE (cpu_features, TBM);
CPU_FEATURE_SET_USABLE (cpu_features, RDTSCP);
CPU_FEATURE_SET_USABLE (cpu_features, WBNOINVD);
+ CPU_FEATURE_SET_USABLE (cpu_features, FZLRM);
+ CPU_FEATURE_SET_USABLE (cpu_features, FSRS);
+ CPU_FEATURE_SET_USABLE (cpu_features, FSRCS);
/* Can we call xgetbv? */
if (CPU_FEATURES_CPU_P (cpu_features, OSXSAVE))
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 394f1c41a6..3ef92b04e8 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -313,6 +313,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define bit_cpu_AVX_VNNI (1u << 4)
#define bit_cpu_AVX512_BF16 (1u << 5)
+#define bit_cpu_FZLRM (1u << 10)
+#define bit_cpu_FSRS (1u << 11)
+#define bit_cpu_FSRCS (1u << 12)
#define bit_cpu_HRESET (1u << 22)
/* COMMON_CPUID_INDEX_19. */
@@ -534,6 +537,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define index_cpu_AVX_VNNI COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_AVX512_BF16 COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FZLRM COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FSRS COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_FSRCS COMMON_CPUID_INDEX_7_ECX_1
#define index_cpu_HRESET COMMON_CPUID_INDEX_7_ECX_1
/* COMMON_CPUID_INDEX_19. */
@@ -755,6 +761,9 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
/* EAX. */
#define reg_AVX_VNNI eax
#define reg_AVX512_BF16 eax
+#define reg_FZLRM eax
+#define reg_FSRS eax
+#define reg_FSRCS eax
#define reg_HRESET eax
/* COMMON_CPUID_INDEX_19. */
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index aacaa49045..667aa27117 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -223,6 +223,9 @@ do_test (void)
CHECK_CPU_FEATURE (WBNOINVD);
CHECK_CPU_FEATURE (AVX_VNNI);
CHECK_CPU_FEATURE (AVX512_BF16);
+ CHECK_CPU_FEATURE (FZLRM);
+ CHECK_CPU_FEATURE (FSRS);
+ CHECK_CPU_FEATURE (FSRCS);
CHECK_CPU_FEATURE (HRESET);
CHECK_CPU_FEATURE (AESKLE);
CHECK_CPU_FEATURE (WIDE_KL);
@@ -380,6 +383,9 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (WBNOINVD);
CHECK_CPU_FEATURE_USABLE (AVX_VNNI);
CHECK_CPU_FEATURE_USABLE (AVX512_BF16);
+ CHECK_CPU_FEATURE_USABLE (FZLRM);
+ CHECK_CPU_FEATURE_USABLE (FSRS);
+ CHECK_CPU_FEATURE_USABLE (FSRCS);
CHECK_CPU_FEATURE_USABLE (AESKLE);
CHECK_CPU_FEATURE_USABLE (WIDE_KL);
--
2.26.2
next prev parent reply other threads:[~2020-10-08 16:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` H.J. Lu via Libc-alpha [this message]
2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha
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