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From: "H.J. Lu via Libc-alpha" <libc-alpha@sourceware.org>
To: libc-alpha@sourceware.org
Subject: [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support
Date: Thu,  8 Oct 2020 09:12:31 -0700	[thread overview]
Message-ID: <20201008161232.135513-5-hjl.tools@gmail.com> (raw)
In-Reply-To: <20201008161232.135513-1-hjl.tools@gmail.com>

Add Intel HRESET support to <sys/platform/x86.h>.
---
 manual/platform.texi               | 3 +++
 sysdeps/x86/sys/platform/x86.h     | 3 +++
 sysdeps/x86/tst-get-cpu-features.c | 1 +
 3 files changed, 7 insertions(+)

diff --git a/manual/platform.texi b/manual/platform.texi
index 283f255679..1e44525552 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -346,6 +346,9 @@ extensions.
 @item
 @code{HTT} -- Max APIC IDs reserved field is Valid.
 
+@item
+@code{HRESET} -- History reset.
+
 @item
 @code{HYBRID} -- Hybrid processor.
 
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 276de1eb6b..394f1c41a6 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -313,6 +313,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
 /* EAX.  */
 #define bit_cpu_AVX_VNNI	(1u << 4)
 #define bit_cpu_AVX512_BF16	(1u << 5)
+#define bit_cpu_HRESET		(1u << 22)
 
 /* COMMON_CPUID_INDEX_19.  */
 
@@ -533,6 +534,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
 /* EAX.  */
 #define index_cpu_AVX_VNNI	COMMON_CPUID_INDEX_7_ECX_1
 #define index_cpu_AVX512_BF16	COMMON_CPUID_INDEX_7_ECX_1
+#define index_cpu_HRESET	COMMON_CPUID_INDEX_7_ECX_1
 
 /* COMMON_CPUID_INDEX_19.  */
 
@@ -753,6 +755,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
 /* EAX.  */
 #define reg_AVX_VNNI		eax
 #define reg_AVX512_BF16		eax
+#define reg_HRESET		eax
 
 /* COMMON_CPUID_INDEX_19.  */
 
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index e87158d45b..aacaa49045 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -223,6 +223,7 @@ do_test (void)
   CHECK_CPU_FEATURE (WBNOINVD);
   CHECK_CPU_FEATURE (AVX_VNNI);
   CHECK_CPU_FEATURE (AVX512_BF16);
+  CHECK_CPU_FEATURE (HRESET);
   CHECK_CPU_FEATURE (AESKLE);
   CHECK_CPU_FEATURE (WIDE_KL);
 
-- 
2.26.2


  parent reply	other threads:[~2020-10-08 16:12 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` H.J. Lu via Libc-alpha [this message]
2020-10-08 16:12 ` [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support H.J. Lu via Libc-alpha
2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha

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