From: "H.J. Lu via Libc-alpha" <libc-alpha@sourceware.org>
To: libc-alpha@sourceware.org
Subject: [PATCH 2/5] <sys/platform/x86.h>: Add AVX512_FP16 support
Date: Thu, 8 Oct 2020 09:12:29 -0700 [thread overview]
Message-ID: <20201008161232.135513-3-hjl.tools@gmail.com> (raw)
In-Reply-To: <20201008161232.135513-1-hjl.tools@gmail.com>
Add AVX512_FP16 support to <sys/platform/x86.h>.
---
manual/platform.texi | 3 +++
sysdeps/x86/cpu-features.c | 2 ++
sysdeps/x86/sys/platform/x86.h | 6 +++---
sysdeps/x86/tst-get-cpu-features.c | 2 ++
4 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/manual/platform.texi b/manual/platform.texi
index 0dd12a4353..4f5fdff9d9 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -210,6 +210,9 @@ The supported processor features are:
@item
@code{AVX512_BITALG} -- The AVX512_BITALG instruction extensions.
+@item
+@code{AVX512_FP16} -- The AVX512_FP16 instruction extensions.
+
@item
@code{AVX512_IFMA} -- The AVX512_IFMA instruction extensions.
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
index 6551df19c0..4ecb8cee2c 100644
--- a/sysdeps/x86/cpu-features.c
+++ b/sysdeps/x86/cpu-features.c
@@ -175,6 +175,8 @@ update_usable (struct cpu_features *cpu_features)
AVX512_VP2INTERSECT);
/* Determine if AVX512_BF16 is usable. */
CPU_FEATURE_SET_USABLE (cpu_features, AVX512_BF16);
+ /* Determine if AVX512_FP16 is usable. */
+ CPU_FEATURE_SET_USABLE (cpu_features, AVX512_FP16);
}
}
}
diff --git a/sysdeps/x86/sys/platform/x86.h b/sysdeps/x86/sys/platform/x86.h
index 22bb28449d..00cd151199 100644
--- a/sysdeps/x86/sys/platform/x86.h
+++ b/sysdeps/x86/sys/platform/x86.h
@@ -259,7 +259,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define bit_cpu_IBT (1u << 20)
#define bit_cpu_INDEX_7_EDX_21 (1u << 21)
#define bit_cpu_AMX_BF16 (1u << 22)
-#define bit_cpu_INDEX_7_EDX_23 (1u << 23)
+#define bit_cpu_AVX512_FP16 (1u << 23)
#define bit_cpu_AMX_TILE (1u << 24)
#define bit_cpu_AMX_INT8 (1u << 25)
#define bit_cpu_IBRS_IBPB (1u << 26)
@@ -478,7 +478,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define index_cpu_IBT COMMON_CPUID_INDEX_7
#define index_cpu_INDEX_7_EDX_21 COMMON_CPUID_INDEX_7
#define index_cpu_AMX_BF16 COMMON_CPUID_INDEX_7
-#define index_cpu_INDEX_7_EDX_23 COMMON_CPUID_INDEX_7
+#define index_cpu_AVX512_FP16 COMMON_CPUID_INDEX_7
#define index_cpu_AMX_TILE COMMON_CPUID_INDEX_7
#define index_cpu_AMX_INT8 COMMON_CPUID_INDEX_7
#define index_cpu_IBRS_IBPB COMMON_CPUID_INDEX_7
@@ -697,7 +697,7 @@ extern const struct cpu_features *__x86_get_cpu_features (unsigned int)
#define reg_IBT edx
#define reg_INDEX_7_EDX_21 edx
#define reg_AMX_BF16 edx
-#define reg_INDEX_7_EDX_23 edx
+#define reg_AVX512_FP16 edx
#define reg_AMX_TILE edx
#define reg_AMX_INT8 edx
#define reg_IBRS_IBPB edx
diff --git a/sysdeps/x86/tst-get-cpu-features.c b/sysdeps/x86/tst-get-cpu-features.c
index d160f7c7a1..7262c3a3fa 100644
--- a/sysdeps/x86/tst-get-cpu-features.c
+++ b/sysdeps/x86/tst-get-cpu-features.c
@@ -191,6 +191,7 @@ do_test (void)
CHECK_CPU_FEATURE (PCONFIG);
CHECK_CPU_FEATURE (IBT);
CHECK_CPU_FEATURE (AMX_BF16);
+ CHECK_CPU_FEATURE (AVX512_FP16);
CHECK_CPU_FEATURE (AMX_TILE);
CHECK_CPU_FEATURE (AMX_INT8);
CHECK_CPU_FEATURE (IBRS_IBPB);
@@ -345,6 +346,7 @@ do_test (void)
CHECK_CPU_FEATURE_USABLE (TSXLDTRK);
CHECK_CPU_FEATURE_USABLE (PCONFIG);
CHECK_CPU_FEATURE_USABLE (AMX_BF16);
+ CHECK_CPU_FEATURE_USABLE (AVX512_FP16);
CHECK_CPU_FEATURE_USABLE (AMX_TILE);
CHECK_CPU_FEATURE_USABLE (AMX_INT8);
CHECK_CPU_FEATURE_USABLE (IBRS_IBPB);
--
2.26.2
next prev parent reply other threads:[~2020-10-08 16:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 16:12 [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 1/5] <sys/platform/x86.h>: Add Intel UINTR support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` H.J. Lu via Libc-alpha [this message]
2020-10-08 16:12 ` [PATCH 3/5] <sys/platform/x86.h>: Add AVX-VNNI support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 4/5] <sys/platform/x86.h>: Add Intel HRESET support H.J. Lu via Libc-alpha
2020-10-08 16:12 ` [PATCH 5/5] <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM support H.J. Lu via Libc-alpha
2020-10-09 16:49 ` [PATCH 0/5] Update <sys/platform/x86.h> for ISE revision 041 H.J. Lu via Libc-alpha
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