From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
To: Hagen SANKOWSKI <hsank@posteo.de>
Cc: "Linux on small ARM machines" <arm-netbook@lists.phcomp.co.uk>,
libresilicon-developers@list.libresilicon.com,
"Discussão do LibrePlanet" <libreplanet-discuss@libreplanet.org>,
"Libre-RISCV General Development"
<libre-riscv-dev@lists.libre-riscv.org>
Subject: Re: [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
Date: Tue, 24 Sep 2019 12:16:04 +0100 [thread overview]
Message-ID: <CAPweEDyokza9700gY+g6ryKvb2C7a9x4FLGDTYe78AHgbd51qw@mail.gmail.com> (raw)
In-Reply-To: <b91017483cee3c925ffe11b1e28a69c6@posteo.de>
On Tue, Sep 24, 2019 at 9:55 AM Hagen SANKOWSKI <hsank@posteo.de> wrote:
> The main difference between AMBI AXI and Wishbone is the streaming
> capability. AXI can stream data, just with repetition stages, without
> handshake signals. So, it would be easier and more sustainable to
> bring-up Wishbone to the next level by standardize a similar streaming
> feature. And yes, there are a lot of cores which using AMBA AXI which
> had to be partly re-written for Wishbone. But currently, there is no
> alternative, or as the German chancellor Merkel likes to say:
> "alternativlos". With added streaming feature to Wishbone, we would get
> an alternative full-featured SoC Bus and Designers could fix their bad
> AMBA AXI bus interfaces..
great: this sounds like a perfect *additional* Research Project which
someone [else] could put in a request for funding. once it is
available, we can look at converting the code over to use it, and
converting any peripherals to use it.
or, if someone [else] wants to include the Libre RISC-V SoC peripheral
set as a possible suite of examples to convert (which would help
justify a budget of EUR 50,000) they are welcome to do so.
the relevance of the streaming capability is that we need an I2S Audio Bus.
i can help with a write-up: unfortunately i am hitting an _additional_
limit of EUR 250,000 per person for overall projects submitted, so
cannot be the one to submit it.
l.
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next prev parent reply other threads:[~2019-09-24 11:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 6:56 NLNet Funding Proposals for the Libre RISC-V SoC: call for participation Luke Kenneth Casson Leighton
2019-09-23 8:48 ` [Libre-silicon-devel] " David Lanzendörfer
2019-09-24 7:43 ` Luke Kenneth Casson Leighton
2019-09-24 8:54 ` Hagen SANKOWSKI
2019-09-24 11:16 ` Luke Kenneth Casson Leighton [this message]
2019-09-24 12:06 ` Staf Verhaegen
2019-09-24 12:12 ` Luke Kenneth Casson Leighton
2019-09-24 12:33 ` Luke Kenneth Casson Leighton
2019-09-25 9:16 ` Luke Kenneth Casson Leighton
2019-09-24 13:43 ` [Libre-silicon-devel] " Staf Verhaegen
2019-09-24 13:53 ` Luke Kenneth Casson Leighton
2020-03-13 0:45 ` Luke Kenneth Casson Leighton
2020-03-13 1:19 ` Adrienne G. Thompson
2020-03-13 1:38 ` [libre-riscv-dev] " Samuel Falvo II
2020-03-13 10:29 ` Luke Kenneth Casson Leighton
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