NLNet Funding Proposals for the Libre RISC-V SoC: call for participation

[Luke Kenneth Casson Leighton <lkcl@lkcl.net>]

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[please do remove all but libre-riscv-dev when replying, thx]

https://libre-riscv.org/nlnet_proposals/

A series of funding proposals, each for EUR 50,000, have been submitted to
NLNet.  These are for charitable donations and may be given to either
individuals or to Universities (not to Corporations) for completion of an
allotted milestone.

The basic idea is to think through and plan for commercial completion all
of the tasks that will make the Libre RISC-V SoC a success. It's a lot! We
have the following:


   - a second Vulkan 3D driver, which will be a port of AMDVLK. similar to
   swiftshader, for the Libre RISCV SoC, except taking into account the
   Vectorisation, predication and custom accelerated opcodes.
   - a video acceleration initiative: with NEON assembler being up to the
   job of decoding 720p video on recent ARM64 processors, the idea is to
   design instructions that will do the job and then follow through getting
   the code upstream.
   - two related proposals which, in combination, will result in an actual
   180nm ASIC being taped out at TSMC.
   - a formal mathematical proof of the hardware design, proving inviolate
   guarantees of its correctness. this because although auditing the code is
   possible, it is both laborious, error prone, and could be compromised.
   mathematical proofs may be run by anyone and are inviolate.
   - an augmentation of gcc to support the processor’s parallel and
   vectorisation capabilities.


Yes, really: 180nm ASICs only cost around EUR 600 per square millimetre,
and with around 20 or so mm^2 it is completely within the realm of
possibility for an NLNet Grant to fund a test ASIC. With each square
millimetre being around 40,000 gates in 180nm, that's around 800,000 gates,
which is enormous.

We would then have a proven ASIC, and moving up to 40nm or below, which
would require around the USD 2m mark, is a far less risky proposition.

The irony is that whilst these funding proposals are quite easy to write,
we also need to find people willing to do the work! In particular, we need
at least one EU Citizen per project. They do not have to be permanently
resident in the EU, they do however need an EU residence. Yes this includes
the UK at the time of writing.

This is an extremely important strategic project that puts you - software
libre developers - in the driving seat of modern technology instead of
picking up the reverse engineering crumbs that fall from the Corporate
table with at least a 2 year delay.

If you would like to help and actually receive donations (directly
transferred) from NLNet for doing so, please do contact me directly or on
libre-riscv-dev.

L.



-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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   [please do remove all but libre-riscv-dev when replying, thx]

   [1]https://libre-riscv.org/nlnet_proposals/

   A series of funding proposals, each for EUR 50,000, have been submitted
   to NLNet.  These are for charitable donations and may be given to
   either individuals or to Universities (not to Corporations) for
   completion of an allotted milestone.

   The basic idea is to think through and plan for commercial completion
   all of the tasks that will make the Libre RISC-V SoC a success. It's a
   lot! We have the following:

     * a second Vulkan 3D driver, which will be a port of AMDVLK. similar
       to swiftshader, for the Libre RISCV SoC, except taking into account
       the Vectorisation, predication and custom accelerated opcodes.
     * a video acceleration initiative: with NEON assembler being up to
       the job of decoding 720p video on recent ARM64 processors, the idea
       is to design instructions that will do the job and then follow
       through getting the code upstream.
     * two related proposals which, in combination, will result in an
       actual 180nm ASIC being taped out at TSMC.
     * a formal mathematical proof of the hardware design, proving
       inviolate guarantees of its correctness. this because although
       auditing the code is possible, it is both laborious, error prone,
       and could be compromised. mathematical proofs may be run by anyone
       and are inviolate.
     * an augmentation of gcc to support the processor’s parallel and
       vectorisation capabilities.

   Yes, really: 180nm ASICs only cost around EUR 600 per square
   millimetre, and with around 20 or so mm^2 it is completely within the
   realm of possibility for an NLNet Grant to fund a test ASIC. With each
   square millimetre being around 40,000 gates in 180nm, that's around
   800,000 gates, which is enormous.

   We would then have a proven ASIC, and moving up to 40nm or below, which
   would require around the USD 2m mark, is a far less risky proposition.

   The irony is that whilst these funding proposals are quite easy to
   write, we also need to find people willing to do the work! In
   particular, we need at least one EU Citizen per project. They do not
   have to be permanently resident in the EU, they do however need an EU
   residence. Yes this includes the UK at the time of writing.

   This is an extremely important strategic project that puts you -
   software libre developers - in the driving seat of modern technology
   instead of picking up the reverse engineering crumbs that fall from the
   Corporate table with at least a 2 year delay.

   If you would like to help and actually receive donations (directly
   transferred) from NLNet for doing so, please do contact me directly or
   on libre-riscv-dev.

   L.

   --
   ---
   crowd-funded eco-conscious hardware:
   [2]https://www.crowdsupply.com/eoma68

References

   1. https://libre-riscv.org/nlnet_proposals/
   2. https://www.crowdsupply.com/eoma68

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