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From: Staf Verhaegen <staf@fibraservi.eu>
To: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Cc: "Linux on small ARM machines" <arm-netbook@lists.phcomp.co.uk>,
	libresilicon-developers@list.libresilicon.com,
	"Discussão do LibrePlanet" <libreplanet-discuss@libreplanet.org>,
	"Libre-RISCV General Development"
	<libre-riscv-dev@lists.libre-riscv.org>,
	"Hagen SANKOWSKI" <hsank@posteo.de>
Subject: Re: [Libre-silicon-devel] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
Date: Tue, 24 Sep 2019 15:43:22 +0200	[thread overview]
Message-ID: <8f38a14422e96826c094f471abcf584591b62c5d.camel@fibraservi.eu> (raw)
In-Reply-To: <CAPweEDzTtSJ8oA93UviHLe80hWTd-nYQGmUdsJ6TWZ8KFeD-VA@mail.gmail.com>


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Luke Kenneth Casson Leighton schreef op di 24-09-2019 om 13:12 [+0100]:
> On Tue, Sep 24, 2019 at 1:06 PM Staf Verhaegen <staf@fibraservi.eu> wrote:
> > Have yo guys looked at the pipeline feature of Wishbone B4 ? What is missing there to make streaming possible ?
> 
> hagen mentioned (offlist) that the broadcast mode of wishbone b4 couldindeed be used.  he'd like to do a write-up / proposal and i am happyto help him review it.
> l.

OK, let me mention I have for my Retro-uC currently nmigen Wishbone code. I use it to make an arbiter between JTAG and the CPU cores on the design (Z80, MOS6502 and Motorola 68000) that can do a read/write for each cycle.
Plan is top commit code to my gitlab repo after ORConf.
Dan from ZipCPU would say that I still have to formally verify the code though... .

greets,
Staf.


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   Luke Kenneth Casson Leighton schreef op di 24-09-2019 om 13:12 [+0100]:

On Tue, Sep 24, 2019 at 1:06 PM Staf Verhaegen <


staf@fibraservi.eu
> wrote:


Have yo guys looked at the pipeline feature of Wishbone B4 ? What is missing the
re to make streaming possible ?



hagen mentioned (offlist) that the broadcast mode of wishbone b4 could
indeed be used.  he'd like to do a write-up / proposal and i am happy
to help him review it.

l.

   OK, let me mention I have for my Retro-uC currently nmigen Wishbone
   code. I use it to make an arbiter between JTAG and the CPU cores on the
   design (Z80, MOS6502 and Motorola 68000) that can do a read/write for
   each cycle.

   Plan is top commit code to my gitlab repo after ORConf.

   Dan from ZipCPU would say that I still have to formally verify the code
   though... .

   greets,

   Staf.

References

   Visible links

   Hidden links:
   2. mailto:staf@fibraservi.eu

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  parent reply	other threads:[~2019-09-24 14:58 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-23  6:56 NLNet Funding Proposals for the Libre RISC-V SoC: call for participation Luke Kenneth Casson Leighton
2019-09-23  8:48 ` [Libre-silicon-devel] " David Lanzendörfer
2019-09-24  7:43   ` Luke Kenneth Casson Leighton
2019-09-24  8:54     ` Hagen SANKOWSKI
2019-09-24 11:16       ` Luke Kenneth Casson Leighton
2019-09-24 12:06         ` Staf Verhaegen
2019-09-24 12:12           ` Luke Kenneth Casson Leighton
2019-09-24 12:33             ` Luke Kenneth Casson Leighton
2019-09-25  9:16               ` Luke Kenneth Casson Leighton
2019-09-24 13:43             ` Staf Verhaegen [this message]
2019-09-24 13:53               ` Luke Kenneth Casson Leighton
2020-03-13  0:45 ` Luke Kenneth Casson Leighton
2020-03-13  1:19   ` Adrienne G. Thompson
2020-03-13  1:38   ` [libre-riscv-dev] " Samuel Falvo II
2020-03-13 10:29     ` Luke Kenneth Casson Leighton

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