* [PATCH 1/8] aarch64/fpu: Add vector variants of erf
@ 2024-02-20 16:59 Joe Ramsay
2024-02-20 16:59 ` [PATCH 2/8] aarch64/fpu: Add vector variants of cosh Joe Ramsay
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 7 +-
sysdeps/aarch64/fpu/Versions | 7 +
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
sysdeps/aarch64/fpu/erf_advsimd.c | 161 ++
sysdeps/aarch64/fpu/erf_data.c | 800 +++++++++
sysdeps/aarch64/fpu/erf_sve.c | 115 ++
sysdeps/aarch64/fpu/erff_advsimd.c | 123 ++
sysdeps/aarch64/fpu/erff_data.c | 544 ++++++
sysdeps/aarch64/fpu/erff_sve.c | 93 +
sysdeps/aarch64/fpu/sv_erf_data.c | 1570 +++++++++++++++++
sysdeps/aarch64/fpu/sv_erff_data.c | 1058 +++++++++++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/fpu/vecmath_config.h | 28 +
sysdeps/aarch64/libm-test-ulps | 8 +
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
19 files changed, 4531 insertions(+), 1 deletion(-)
create mode 100644 sysdeps/aarch64/fpu/erf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/erf_data.c
create mode 100644 sysdeps/aarch64/fpu/erf_sve.c
create mode 100644 sysdeps/aarch64/fpu/erff_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/erff_data.c
create mode 100644 sysdeps/aarch64/fpu/erff_sve.c
create mode 100644 sysdeps/aarch64/fpu/sv_erf_data.c
create mode 100644 sysdeps/aarch64/fpu/sv_erff_data.c
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index 1fe4b52682..320b6ed43a 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -3,6 +3,7 @@ libmvec-supported-funcs = acos \
atan \
atan2 \
cos \
+ erf \
exp \
exp10 \
exp2 \
@@ -27,7 +28,11 @@ libmvec-support = $(addsuffix f_advsimd,$(float-advsimd-funcs)) \
v_log_data \
v_exp_data \
v_log2_data \
- v_log10_data
+ v_log10_data \
+ erf_data \
+ erff_data \
+ sv_erf_data \
+ sv_erff_data
endif
sve-cflags = -march=armv8-a+sve
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index accd101184..d7b1e87191 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -78,4 +78,11 @@ libmvec {
_ZGVsMxv_tanf;
_ZGVsMxv_tan;
}
+ GLIBC_2.40 {
+ _ZGVnN2v_erf;
+ _ZGVnN2v_erff;
+ _ZGVnN4v_erff;
+ _ZGVsMxv_erf;
+ _ZGVsMxv_erff;
+ }
}
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index 8fec7a4b44..d8d88de218 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -21,6 +21,7 @@ libmvec_hidden_proto (V_NAME_F1(acos));
libmvec_hidden_proto (V_NAME_F1(asin));
libmvec_hidden_proto (V_NAME_F1(atan));
libmvec_hidden_proto (V_NAME_F1(cos));
+libmvec_hidden_proto (V_NAME_F1(erf));
libmvec_hidden_proto (V_NAME_F1(exp10));
libmvec_hidden_proto (V_NAME_F1(exp2));
libmvec_hidden_proto (V_NAME_F1(exp));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 04837bdcd7..71f53363a0 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -49,6 +49,10 @@
# define __DECL_SIMD_cos __DECL_SIMD_aarch64
# undef __DECL_SIMD_cosf
# define __DECL_SIMD_cosf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_erf
+# define __DECL_SIMD_erf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_erff
+# define __DECL_SIMD_erff __DECL_SIMD_aarch64
# undef __DECL_SIMD_exp
# define __DECL_SIMD_exp __DECL_SIMD_aarch64
# undef __DECL_SIMD_expf
@@ -120,6 +124,7 @@ __vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_erff (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t);
@@ -136,6 +141,7 @@ __vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_erf (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp2 (__f64x2_t);
@@ -157,6 +163,7 @@ __sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_erff (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_exp2f (__sv_f32_t, __sv_bool_t);
@@ -173,6 +180,7 @@ __sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_erf (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp2 (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/erf_advsimd.c b/sysdeps/aarch64/fpu/erf_advsimd.c
new file mode 100644
index 0000000000..3e70cbc025
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erf_advsimd.c
@@ -0,0 +1,161 @@
+/* Double-precision vector (Advanced SIMD) erf function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+
+static const struct data
+{
+ float64x2_t third;
+ float64x2_t tenth, two_over_five, two_over_fifteen;
+ float64x2_t two_over_nine, two_over_fortyfive;
+ float64x2_t max, shift;
+#if WANT_SIMD_EXCEPT
+ float64x2_t tiny_bound, huge_bound, scale_minus_one;
+#endif
+} data = {
+ .third = V2 (0x1.5555555555556p-2), /* used to compute 2/3 and 1/6 too. */
+ .two_over_fifteen = V2 (0x1.1111111111111p-3),
+ .tenth = V2 (-0x1.999999999999ap-4),
+ .two_over_five = V2 (-0x1.999999999999ap-2),
+ .two_over_nine = V2 (-0x1.c71c71c71c71cp-3),
+ .two_over_fortyfive = V2 (0x1.6c16c16c16c17p-5),
+ .max = V2 (5.9921875), /* 6 - 1/128. */
+ .shift = V2 (0x1p45),
+#if WANT_SIMD_EXCEPT
+ .huge_bound = V2 (0x1p205),
+ .tiny_bound = V2 (0x1p-226),
+ .scale_minus_one = V2 (0x1.06eba8214db69p-3), /* 2/sqrt(pi) - 1.0. */
+#endif
+};
+
+#define AbsMask 0x7fffffffffffffff
+
+struct entry
+{
+ float64x2_t erf;
+ float64x2_t scale;
+};
+
+static inline struct entry
+lookup (uint64x2_t i)
+{
+ struct entry e;
+ float64x2_t e1 = vld1q_f64 ((float64_t *) (__erf_data.tab + i[0])),
+ e2 = vld1q_f64 ((float64_t *) (__erf_data.tab + i[1]));
+ e.erf = vuzp1q_f64 (e1, e2);
+ e.scale = vuzp2q_f64 (e1, e2);
+ return e;
+}
+
+/* Double-precision implementation of vector erf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erf(x) ~ erf(r) + scale * d * [
+ + 1
+ - r d
+ + 1/3 (2 r^2 - 1) d^2
+ - 1/6 (r (2 r^2 - 3)) d^3
+ + 1/30 (4 r^4 - 12 r^2 + 3) d^4
+ - 1/90 (4 r^4 - 20 r^2 + 15) d^5
+ ]
+
+ Maximum measure error: 2.29 ULP
+ V_NAME_D1 (erf)(-0x1.00003c924e5d1p-8) got -0x1.20dd59132ebadp-8
+ want -0x1.20dd59132ebafp-8. */
+float64x2_t VPCS_ATTR V_NAME_D1 (erf) (float64x2_t x)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+ float64x2_t a = vabsq_f64 (x);
+ /* Reciprocal conditions that do not catch NaNs so they can be used in BSLs
+ to return expected results. */
+ uint64x2_t a_le_max = vcleq_f64 (a, dat->max);
+ uint64x2_t a_gt_max = vcgtq_f64 (a, dat->max);
+
+#if WANT_SIMD_EXCEPT
+ /* |x| huge or tiny. */
+ uint64x2_t cmp1 = vcgtq_f64 (a, dat->huge_bound);
+ uint64x2_t cmp2 = vcltq_f64 (a, dat->tiny_bound);
+ uint64x2_t cmp = vorrq_u64 (cmp1, cmp2);
+ /* If any lanes are special, mask them with 1 for small x or 8 for large
+ values and retain a copy of a to allow special case handler to fix special
+ lanes later. This is only necessary if fenv exceptions are to be triggered
+ correctly. */
+ if (__glibc_unlikely (v_any_u64 (cmp)))
+ {
+ a = vbslq_f64 (cmp1, v_f64 (8.0), a);
+ a = vbslq_f64 (cmp2, v_f64 (1.0), a);
+ }
+#endif
+
+ /* Set r to multiple of 1/128 nearest to |x|. */
+ float64x2_t shift = dat->shift;
+ float64x2_t z = vaddq_f64 (a, shift);
+
+ /* Lookup erf(r) and scale(r) in table, without shortcut for small values,
+ but with saturated indices for large values and NaNs in order to avoid
+ segfault. */
+ uint64x2_t i
+ = vsubq_u64 (vreinterpretq_u64_f64 (z), vreinterpretq_u64_f64 (shift));
+ i = vbslq_u64 (a_le_max, i, v_u64 (768));
+ struct entry e = lookup (i);
+
+ float64x2_t r = vsubq_f64 (z, shift);
+
+ /* erf(x) ~ erf(r) + scale * d * poly (r, d). */
+ float64x2_t d = vsubq_f64 (a, r);
+ float64x2_t d2 = vmulq_f64 (d, d);
+ float64x2_t r2 = vmulq_f64 (r, r);
+
+ /* poly (d, r) = 1 + p1(r) * d + p2(r) * d^2 + ... + p5(r) * d^5. */
+ float64x2_t p1 = r;
+ float64x2_t p2
+ = vfmsq_f64 (dat->third, r2, vaddq_f64 (dat->third, dat->third));
+ float64x2_t p3 = vmulq_f64 (r, vfmaq_f64 (v_f64 (-0.5), r2, dat->third));
+ float64x2_t p4 = vfmaq_f64 (dat->two_over_five, r2, dat->two_over_fifteen);
+ p4 = vfmsq_f64 (dat->tenth, r2, p4);
+ float64x2_t p5 = vfmaq_f64 (dat->two_over_nine, r2, dat->two_over_fortyfive);
+ p5 = vmulq_f64 (r, vfmaq_f64 (vmulq_f64 (v_f64 (0.5), dat->third), r2, p5));
+
+ float64x2_t p34 = vfmaq_f64 (p3, d, p4);
+ float64x2_t p12 = vfmaq_f64 (p1, d, p2);
+ float64x2_t y = vfmaq_f64 (p34, d2, p5);
+ y = vfmaq_f64 (p12, d2, y);
+
+ y = vfmaq_f64 (e.erf, e.scale, vfmsq_f64 (d, d2, y));
+
+ /* Solves the |x| = inf and NaN cases. */
+ y = vbslq_f64 (a_gt_max, v_f64 (1.0), y);
+
+ /* Copy sign. */
+ y = vbslq_f64 (v_u64 (AbsMask), y, x);
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u64 (cmp2)))
+ {
+ /* Neutralise huge values of x before fixing small values. */
+ x = vbslq_f64 (cmp1, v_f64 (1.0), x);
+ /* Fix tiny values that trigger spurious underflow. */
+ return vbslq_f64 (cmp2, vfmaq_f64 (x, dat->scale_minus_one, x), y);
+ }
+#endif
+ return y;
+}
diff --git a/sysdeps/aarch64/fpu/erf_data.c b/sysdeps/aarch64/fpu/erf_data.c
new file mode 100644
index 0000000000..6d2dcd235c
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erf_data.c
@@ -0,0 +1,800 @@
+/* Table for Advanced SIMD erf approximation
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in erf.
+ For each possible rounded input r (multiples of 1/128), between
+ r = 0.0 and r = 6.0 (769 values):
+ - the first entry __erff_data.tab.erf contains the values of erf(r),
+ - the second entry __erff_data.tab.scale contains the values of
+ 2/sqrt(pi)*exp(-r^2). Note that indices 0 and 1 are never hit by the
+ algorithm, since lookup is performed only for x >= 1/64-1/512. */
+const struct erf_data __erf_data = {
+ .tab = { { 0x0.0000000000000p+0, 0x1.20dd750429b6dp+0 },
+ { 0x1.20dbf3deb1340p-7, 0x1.20d8f1975c85dp+0 },
+ { 0x1.20d77083f17a0p-6, 0x1.20cb67bd452c7p+0 },
+ { 0x1.b137e0cf584dcp-6, 0x1.20b4d8bac36c1p+0 },
+ { 0x1.20c5645dd2538p-5, 0x1.209546ad13ccfp+0 },
+ { 0x1.68e5d3bbc9526p-5, 0x1.206cb4897b148p+0 },
+ { 0x1.b0fafef135745p-5, 0x1.203b261cd0052p+0 },
+ { 0x1.f902a77bd3821p-5, 0x1.2000a00ae3804p+0 },
+ { 0x1.207d480e90658p-4, 0x1.1fbd27cdc72d3p+0 },
+ { 0x1.44703e87e8593p-4, 0x1.1f70c3b4f2cc7p+0 },
+ { 0x1.68591a1e83b5dp-4, 0x1.1f1b7ae44867fp+0 },
+ { 0x1.8c36beb8a8d23p-4, 0x1.1ebd5552f795bp+0 },
+ { 0x1.b0081148a873ap-4, 0x1.1e565bca400d4p+0 },
+ { 0x1.d3cbf7e70a4b3p-4, 0x1.1de697e413d28p+0 },
+ { 0x1.f78159ec8bb50p-4, 0x1.1d6e14099944ap+0 },
+ { 0x1.0d939005f65e5p-3, 0x1.1cecdb718d61cp+0 },
+ { 0x1.1f5e1a35c3b89p-3, 0x1.1c62fa1e869b6p+0 },
+ { 0x1.311fc15f56d14p-3, 0x1.1bd07cdd189acp+0 },
+ { 0x1.42d7fc2f64959p-3, 0x1.1b357141d95d5p+0 },
+ { 0x1.548642321d7c6p-3, 0x1.1a91e5a748165p+0 },
+ { 0x1.662a0bdf7a89fp-3, 0x1.19e5e92b964abp+0 },
+ { 0x1.77c2d2a765f9ep-3, 0x1.19318bae53a04p+0 },
+ { 0x1.895010fdbdbfdp-3, 0x1.1874ddcdfce24p+0 },
+ { 0x1.9ad142662e14dp-3, 0x1.17aff0e56ec10p+0 },
+ { 0x1.ac45e37fe2526p-3, 0x1.16e2d7093cd8cp+0 },
+ { 0x1.bdad72110a648p-3, 0x1.160da304ed92fp+0 },
+ { 0x1.cf076d1233237p-3, 0x1.153068581b781p+0 },
+ { 0x1.e05354b96ff36p-3, 0x1.144b3b337c90cp+0 },
+ { 0x1.f190aa85540e2p-3, 0x1.135e3075d076bp+0 },
+ { 0x1.015f78a3dcf3dp-2, 0x1.12695da8b5bdep+0 },
+ { 0x1.09eed6982b948p-2, 0x1.116cd8fd67618p+0 },
+ { 0x1.127631eb8de32p-2, 0x1.1068b94962e5ep+0 },
+ { 0x1.1af54e232d609p-2, 0x1.0f5d1602f7e41p+0 },
+ { 0x1.236bef825d9a2p-2, 0x1.0e4a073dc1b91p+0 },
+ { 0x1.2bd9db0f7827fp-2, 0x1.0d2fa5a70c168p+0 },
+ { 0x1.343ed6989b7d9p-2, 0x1.0c0e0a8223359p+0 },
+ { 0x1.3c9aa8b84bedap-2, 0x1.0ae54fa490722p+0 },
+ { 0x1.44ed18d9f6462p-2, 0x1.09b58f724416bp+0 },
+ { 0x1.4d35ef3e5372ep-2, 0x1.087ee4d9ad247p+0 },
+ { 0x1.5574f4ffac98ep-2, 0x1.07416b4fbfe7cp+0 },
+ { 0x1.5da9f415ff23fp-2, 0x1.05fd3ecbec297p+0 },
+ { 0x1.65d4b75b00471p-2, 0x1.04b27bc403d30p+0 },
+ { 0x1.6df50a8dff772p-2, 0x1.03613f2812dafp+0 },
+ { 0x1.760aba57a76bfp-2, 0x1.0209a65e29545p+0 },
+ { 0x1.7e15944d9d3e4p-2, 0x1.00abcf3e187a9p+0 },
+ { 0x1.861566f5fd3c0p-2, 0x1.fe8fb01a47307p-1 },
+ { 0x1.8e0a01cab516bp-2, 0x1.fbbbbef34b4b2p-1 },
+ { 0x1.95f3353cbb146p-2, 0x1.f8dc092d58ff8p-1 },
+ { 0x1.9dd0d2b721f39p-2, 0x1.f5f0cdaf15313p-1 },
+ { 0x1.a5a2aca209394p-2, 0x1.f2fa4c16c0019p-1 },
+ { 0x1.ad68966569a87p-2, 0x1.eff8c4b1375dbp-1 },
+ { 0x1.b522646bbda68p-2, 0x1.ecec7870ebca7p-1 },
+ { 0x1.bccfec24855b8p-2, 0x1.e9d5a8e4c934ep-1 },
+ { 0x1.c4710406a65fcp-2, 0x1.e6b4982f158b9p-1 },
+ { 0x1.cc058392a6d2dp-2, 0x1.e38988fc46e72p-1 },
+ { 0x1.d38d4354c3bd0p-2, 0x1.e054be79d3042p-1 },
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+ { 0x1.ffffffb127525p-1, 0x1.4980cb3c80949p-24 },
+ { 0x1.ffffffb624592p-1, 0x1.3537f00b6ad4dp-24 },
+ { 0x1.ffffffbad2affp-1, 0x1.2225b12bffc68p-24 },
+ { 0x1.ffffffbf370cdp-1, 0x1.10380e1adb7e9p-24 },
+ { 0x1.ffffffc355dfdp-1, 0x1.febc107d5efaap-25 },
+ { 0x1.ffffffc733572p-1, 0x1.df0f2a0ee6946p-25 },
+ { 0x1.ffffffcad3626p-1, 0x1.c14b2188bcee4p-25 },
+ { 0x1.ffffffce39b67p-1, 0x1.a553644f7f07dp-25 },
+ { 0x1.ffffffd169d0cp-1, 0x1.8b0cfce0579dfp-25 },
+ { 0x1.ffffffd466fa5p-1, 0x1.725e7c5dd20f7p-25 },
+ { 0x1.ffffffd7344aap-1, 0x1.5b2fe547a1340p-25 },
+ { 0x1.ffffffd9d4aabp-1, 0x1.456a974e92e93p-25 },
+ { 0x1.ffffffdc4ad7ap-1, 0x1.30f93c3699078p-25 },
+ { 0x1.ffffffde9964ep-1, 0x1.1dc7b5b978cf8p-25 },
+ { 0x1.ffffffe0c2bf0p-1, 0x1.0bc30c5d52f15p-25 },
+ { 0x1.ffffffe2c92dbp-1, 0x1.f5b2be65a0c7fp-26 },
+ { 0x1.ffffffe4aed5ep-1, 0x1.d5f3a8dea7357p-26 },
+ { 0x1.ffffffe675bbdp-1, 0x1.b82915b03515bp-26 },
+ { 0x1.ffffffe81fc4ep-1, 0x1.9c3517e789488p-26 },
+ { 0x1.ffffffe9aeb97p-1, 0x1.81fb7df06136ep-26 },
+ { 0x1.ffffffeb24467p-1, 0x1.6961b8d641d06p-26 },
+ { 0x1.ffffffec81ff2p-1, 0x1.524ec4d916caep-26 },
+ { 0x1.ffffffedc95e7p-1, 0x1.3cab1343d18d1p-26 },
+ { 0x1.ffffffeefbc85p-1, 0x1.2860757487a01p-26 },
+ { 0x1.fffffff01a8b6p-1, 0x1.155a09065d4f7p-26 },
+ { 0x1.fffffff126e1ep-1, 0x1.0384250e4c9fcp-26 },
+ { 0x1.fffffff221f30p-1, 0x1.e59890b926c78p-27 },
+ { 0x1.fffffff30cd3fp-1, 0x1.c642116a8a9e3p-27 },
+ { 0x1.fffffff3e8892p-1, 0x1.a8e405e651ab6p-27 },
+ { 0x1.fffffff4b606fp-1, 0x1.8d5f98114f872p-27 },
+ { 0x1.fffffff57632dp-1, 0x1.7397c5a66e307p-27 },
+ { 0x1.fffffff629e44p-1, 0x1.5b71456c5a4c4p-27 },
+ { 0x1.fffffff6d1e56p-1, 0x1.44d26de513197p-27 },
+ { 0x1.fffffff76ef3fp-1, 0x1.2fa31d6371537p-27 },
+ { 0x1.fffffff801c1fp-1, 0x1.1bcca373b7b43p-27 },
+ { 0x1.fffffff88af67p-1, 0x1.0939ab853339fp-27 },
+ { 0x1.fffffff90b2e3p-1, 0x1.efac5187b2863p-28 },
+ { 0x1.fffffff982fc1p-1, 0x1.cf1e86235d0e6p-28 },
+ { 0x1.fffffff9f2e9fp-1, 0x1.b0a68a2128babp-28 },
+ { 0x1.fffffffa5b790p-1, 0x1.9423165bc4444p-28 },
+ { 0x1.fffffffabd229p-1, 0x1.7974e743dea3cp-28 },
+ { 0x1.fffffffb18582p-1, 0x1.607e9eacd1050p-28 },
+ { 0x1.fffffffb6d844p-1, 0x1.4924a74dec728p-28 },
+ { 0x1.fffffffbbd0aap-1, 0x1.334d19e0c2160p-28 },
+ { 0x1.fffffffc0748fp-1, 0x1.1edfa3c5f5ccap-28 },
+ { 0x1.fffffffc4c96cp-1, 0x1.0bc56f1b54701p-28 },
+ { 0x1.fffffffc8d462p-1, 0x1.f3d2185e047d9p-29 },
+ { 0x1.fffffffcc9a41p-1, 0x1.d26cb87945e87p-29 },
+ { 0x1.fffffffd01f89p-1, 0x1.b334fac4b9f99p-29 },
+ { 0x1.fffffffd36871p-1, 0x1.96076f7918d1cp-29 },
+ { 0x1.fffffffd678edp-1, 0x1.7ac2d72fc2c63p-29 },
+ { 0x1.fffffffd954aep-1, 0x1.614801550319ep-29 },
+ { 0x1.fffffffdbff2ap-1, 0x1.4979ac8b28926p-29 },
+ { 0x1.fffffffde7ba0p-1, 0x1.333c68e2d0548p-29 },
+ { 0x1.fffffffe0cd16p-1, 0x1.1e767bce37dd7p-29 },
+ { 0x1.fffffffe2f664p-1, 0x1.0b0fc5b6d05a0p-29 },
+ { 0x1.fffffffe4fa30p-1, 0x1.f1e3523b41d7dp-30 },
+ { 0x1.fffffffe6daf7p-1, 0x1.d00de6608effep-30 },
+ { 0x1.fffffffe89b0cp-1, 0x1.b0778b7b3301ap-30 },
+ { 0x1.fffffffea3c9ap-1, 0x1.92fb04ec0f6cfp-30 },
+ { 0x1.fffffffebc1a9p-1, 0x1.77756ec9f78fap-30 },
+ { 0x1.fffffffed2c21p-1, 0x1.5dc61922d5a06p-30 },
+ { 0x1.fffffffee7dc8p-1, 0x1.45ce65699ff6dp-30 },
+ { 0x1.fffffffefb847p-1, 0x1.2f71a5f159970p-30 },
+ { 0x1.ffffffff0dd2bp-1, 0x1.1a94ff571654fp-30 },
+ { 0x1.ffffffff1ede9p-1, 0x1.071f4bbea09ecp-30 },
+ { 0x1.ffffffff2ebdap-1, 0x1.e9f1ff8ddd774p-31 },
+ { 0x1.ffffffff3d843p-1, 0x1.c818223a202c7p-31 },
+ { 0x1.ffffffff4b453p-1, 0x1.a887bd2b4404dp-31 },
+ { 0x1.ffffffff58126p-1, 0x1.8b1a336c5eb6bp-31 },
+ { 0x1.ffffffff63fc3p-1, 0x1.6fab63324088ap-31 },
+ { 0x1.ffffffff6f121p-1, 0x1.56197e30205bap-31 },
+ { 0x1.ffffffff79626p-1, 0x1.3e44e45301b92p-31 },
+ { 0x1.ffffffff82fabp-1, 0x1.281000bfe4c3fp-31 },
+ { 0x1.ffffffff8be77p-1, 0x1.135f28f2d50b4p-31 },
+ { 0x1.ffffffff94346p-1, 0x1.00187dded5975p-31 },
+ { 0x1.ffffffff9bec8p-1, 0x1.dc479de0ef001p-32 },
+ { 0x1.ffffffffa319fp-1, 0x1.bad4fdad3caa1p-32 },
+ { 0x1.ffffffffa9c63p-1, 0x1.9baed3ed27ab8p-32 },
+ { 0x1.ffffffffaffa4p-1, 0x1.7ead9ce4285bbp-32 },
+ { 0x1.ffffffffb5be5p-1, 0x1.63ac6b4edc88ep-32 },
+ { 0x1.ffffffffbb1a2p-1, 0x1.4a88be2a6390cp-32 },
+ { 0x1.ffffffffc014ep-1, 0x1.332259185f1a0p-32 },
+ { 0x1.ffffffffc4b56p-1, 0x1.1d5b1f3793044p-32 },
+ { 0x1.ffffffffc901cp-1, 0x1.0916f04b6e18bp-32 },
+ { 0x1.ffffffffccfffp-1, 0x1.ec77101de6926p-33 },
+ { 0x1.ffffffffd0b56p-1, 0x1.c960bf23153e0p-33 },
+ { 0x1.ffffffffd4271p-1, 0x1.a8bd20fc65ef7p-33 },
+ { 0x1.ffffffffd759dp-1, 0x1.8a61745ec7d1dp-33 },
+ { 0x1.ffffffffda520p-1, 0x1.6e25d0e756261p-33 },
+ { 0x1.ffffffffdd13cp-1, 0x1.53e4f7d1666cbp-33 },
+ { 0x1.ffffffffdfa2dp-1, 0x1.3b7c27a7ddb0ep-33 },
+ { 0x1.ffffffffe202dp-1, 0x1.24caf2c32af14p-33 },
+ { 0x1.ffffffffe4371p-1, 0x1.0fb3186804d0fp-33 },
+ { 0x1.ffffffffe642ap-1, 0x1.f830c0bb41fd7p-34 },
+ { 0x1.ffffffffe8286p-1, 0x1.d3c0f1a91c846p-34 },
+ { 0x1.ffffffffe9eb0p-1, 0x1.b1e5acf351d87p-34 },
+ { 0x1.ffffffffeb8d0p-1, 0x1.92712d259ce66p-34 },
+ { 0x1.ffffffffed10ap-1, 0x1.7538c60a04476p-34 },
+ { 0x1.ffffffffee782p-1, 0x1.5a14b04b47879p-34 },
+ { 0x1.ffffffffefc57p-1, 0x1.40dfd87456f4cp-34 },
+ { 0x1.fffffffff0fa7p-1, 0x1.2977b1172b9d5p-34 },
+ { 0x1.fffffffff218fp-1, 0x1.13bc07e891491p-34 },
+ { 0x1.fffffffff3227p-1, 0x1.ff1dbb4300811p-35 },
+ { 0x1.fffffffff4188p-1, 0x1.d9a880f306bd8p-35 },
+ { 0x1.fffffffff4fc9p-1, 0x1.b6e45220b55e0p-35 },
+ { 0x1.fffffffff5cfdp-1, 0x1.96a0b33f2c4dap-35 },
+ { 0x1.fffffffff6939p-1, 0x1.78b07e9e924acp-35 },
+ { 0x1.fffffffff748ep-1, 0x1.5ce9ab1670dd2p-35 },
+ { 0x1.fffffffff7f0dp-1, 0x1.4325167006bb0p-35 },
+ { 0x1.fffffffff88c5p-1, 0x1.2b3e53538ff3fp-35 },
+ { 0x1.fffffffff91c6p-1, 0x1.15137a7f44864p-35 },
+ { 0x1.fffffffff9a1bp-1, 0x1.0084ff125639dp-35 },
+ { 0x1.fffffffffa1d2p-1, 0x1.daeb0b7311ec7p-36 },
+ { 0x1.fffffffffa8f6p-1, 0x1.b7937d1c40c52p-36 },
+ { 0x1.fffffffffaf92p-1, 0x1.96d082f59ab06p-36 },
+ { 0x1.fffffffffb5b0p-1, 0x1.7872d9fa10aadp-36 },
+ { 0x1.fffffffffbb58p-1, 0x1.5c4e8e37bc7d0p-36 },
+ { 0x1.fffffffffc095p-1, 0x1.423ac0df49a40p-36 },
+ { 0x1.fffffffffc56dp-1, 0x1.2a117230ad284p-36 },
+ { 0x1.fffffffffc9e8p-1, 0x1.13af4f04f9998p-36 },
+ { 0x1.fffffffffce0dp-1, 0x1.fde703724e560p-37 },
+ { 0x1.fffffffffd1e1p-1, 0x1.d77f0c82e7641p-37 },
+ { 0x1.fffffffffd56cp-1, 0x1.b3ee02611d7ddp-37 },
+ { 0x1.fffffffffd8b3p-1, 0x1.92ff33023d5bdp-37 },
+ { 0x1.fffffffffdbbap-1, 0x1.7481a9e69f53fp-37 },
+ { 0x1.fffffffffde86p-1, 0x1.5847eda620959p-37 },
+ { 0x1.fffffffffe11dp-1, 0x1.3e27c1fcc74bdp-37 },
+ { 0x1.fffffffffe380p-1, 0x1.25f9ee0b923dcp-37 },
+ { 0x1.fffffffffe5b6p-1, 0x1.0f9a0686531ffp-37 },
+ { 0x1.fffffffffe7c0p-1, 0x1.f5cc7718082afp-38 },
+ { 0x1.fffffffffe9a2p-1, 0x1.cf7e53d6a2ca5p-38 },
+ { 0x1.fffffffffeb60p-1, 0x1.ac0f5f3229372p-38 },
+ { 0x1.fffffffffecfbp-1, 0x1.8b498644847eap-38 },
+ { 0x1.fffffffffee77p-1, 0x1.6cfa9bcca59dcp-38 },
+ { 0x1.fffffffffefd6p-1, 0x1.50f411d4fd2cdp-38 },
+ { 0x1.ffffffffff11ap-1, 0x1.370ab8327af5ep-38 },
+ { 0x1.ffffffffff245p-1, 0x1.1f167f88c6b6ep-38 },
+ { 0x1.ffffffffff359p-1, 0x1.08f24085d4597p-38 },
+ { 0x1.ffffffffff457p-1, 0x1.e8f70e181d619p-39 },
+ { 0x1.ffffffffff542p-1, 0x1.c324c20e337dcp-39 },
+ { 0x1.ffffffffff61bp-1, 0x1.a03261574b54ep-39 },
+ { 0x1.ffffffffff6e3p-1, 0x1.7fe903cdf5855p-39 },
+ { 0x1.ffffffffff79bp-1, 0x1.6215c58da3450p-39 },
+ { 0x1.ffffffffff845p-1, 0x1.46897d4b69fc6p-39 },
+ { 0x1.ffffffffff8e2p-1, 0x1.2d1877d731b7bp-39 },
+ { 0x1.ffffffffff973p-1, 0x1.159a386b11517p-39 },
+ { 0x1.ffffffffff9f8p-1, 0x1.ffd27ae9393cep-40 },
+ { 0x1.ffffffffffa73p-1, 0x1.d7c593130dd0bp-40 },
+ { 0x1.ffffffffffae4p-1, 0x1.b2cd607c79bcfp-40 },
+ { 0x1.ffffffffffb4cp-1, 0x1.90ae4d3405651p-40 },
+ { 0x1.ffffffffffbadp-1, 0x1.71312dd1759e2p-40 },
+ { 0x1.ffffffffffc05p-1, 0x1.5422ef5d8949dp-40 },
+ { 0x1.ffffffffffc57p-1, 0x1.39544b0ecc957p-40 },
+ { 0x1.ffffffffffca2p-1, 0x1.20997f73e73ddp-40 },
+ { 0x1.ffffffffffce7p-1, 0x1.09ca0eaacd277p-40 },
+ { 0x1.ffffffffffd27p-1, 0x1.e9810295890ecp-41 },
+ { 0x1.ffffffffffd62p-1, 0x1.c2b45b5aa4a1dp-41 },
+ { 0x1.ffffffffffd98p-1, 0x1.9eee068fa7596p-41 },
+ { 0x1.ffffffffffdcap-1, 0x1.7df2b399c10a8p-41 },
+ { 0x1.ffffffffffdf8p-1, 0x1.5f8b87a31bd85p-41 },
+ { 0x1.ffffffffffe22p-1, 0x1.4385c96e9a2d9p-41 },
+ { 0x1.ffffffffffe49p-1, 0x1.29b2933ef4cbcp-41 },
+ { 0x1.ffffffffffe6cp-1, 0x1.11e68a6378f8ap-41 },
+ { 0x1.ffffffffffe8dp-1, 0x1.f7f338086a86bp-42 },
+ { 0x1.ffffffffffeabp-1, 0x1.cf8d7d9ce040ap-42 },
+ { 0x1.ffffffffffec7p-1, 0x1.aa577251ae484p-42 },
+ { 0x1.ffffffffffee1p-1, 0x1.8811d739efb5ep-42 },
+ { 0x1.ffffffffffef8p-1, 0x1.68823e52970bep-42 },
+ { 0x1.fffffffffff0ep-1, 0x1.4b72ae68e8b4cp-42 },
+ { 0x1.fffffffffff22p-1, 0x1.30b14dbe876bcp-42 },
+ { 0x1.fffffffffff34p-1, 0x1.181012ef86610p-42 },
+ { 0x1.fffffffffff45p-1, 0x1.01647ba798744p-42 },
+ { 0x1.fffffffffff54p-1, 0x1.d90e917701675p-43 },
+ { 0x1.fffffffffff62p-1, 0x1.b2a87e86d0c8ap-43 },
+ { 0x1.fffffffffff6fp-1, 0x1.8f53dcb377293p-43 },
+ { 0x1.fffffffffff7bp-1, 0x1.6ed2f2515e933p-43 },
+ { 0x1.fffffffffff86p-1, 0x1.50ecc9ed47f19p-43 },
+ { 0x1.fffffffffff90p-1, 0x1.356cd5ce7799ep-43 },
+ { 0x1.fffffffffff9ap-1, 0x1.1c229a587ab78p-43 },
+ { 0x1.fffffffffffa2p-1, 0x1.04e15ecc7f3f6p-43 },
+ { 0x1.fffffffffffaap-1, 0x1.deffc7e6a6017p-44 },
+ { 0x1.fffffffffffb1p-1, 0x1.b7b040832f310p-44 },
+ { 0x1.fffffffffffb8p-1, 0x1.938e021f36d76p-44 },
+ { 0x1.fffffffffffbep-1, 0x1.7258610b3b233p-44 },
+ { 0x1.fffffffffffc3p-1, 0x1.53d3bfc82a909p-44 },
+ { 0x1.fffffffffffc8p-1, 0x1.37c92babdc2fdp-44 },
+ { 0x1.fffffffffffcdp-1, 0x1.1e06010120f6ap-44 },
+ { 0x1.fffffffffffd1p-1, 0x1.065b9616170d4p-44 },
+ { 0x1.fffffffffffd5p-1, 0x1.e13dd96b3753ap-45 },
+ { 0x1.fffffffffffd9p-1, 0x1.b950d32467392p-45 },
+ { 0x1.fffffffffffdcp-1, 0x1.94a72263259a5p-45 },
+ { 0x1.fffffffffffdfp-1, 0x1.72fd93e036cdcp-45 },
+ { 0x1.fffffffffffe2p-1, 0x1.54164576929abp-45 },
+ { 0x1.fffffffffffe4p-1, 0x1.37b83c521fe96p-45 },
+ { 0x1.fffffffffffe7p-1, 0x1.1daf033182e96p-45 },
+ { 0x1.fffffffffffe9p-1, 0x1.05ca50205d26ap-45 },
+ { 0x1.fffffffffffebp-1, 0x1.dfbb6235639fap-46 },
+ { 0x1.fffffffffffedp-1, 0x1.b7807e294781fp-46 },
+ { 0x1.fffffffffffeep-1, 0x1.9298add70a734p-46 },
+ { 0x1.ffffffffffff0p-1, 0x1.70beaf9c7ffb6p-46 },
+ { 0x1.ffffffffffff1p-1, 0x1.51b2cd6709222p-46 },
+ { 0x1.ffffffffffff3p-1, 0x1.353a6cf7f7fffp-46 },
+ { 0x1.ffffffffffff4p-1, 0x1.1b1fa8cbe84a7p-46 },
+ { 0x1.ffffffffffff5p-1, 0x1.0330f0fd69921p-46 },
+ { 0x1.ffffffffffff6p-1, 0x1.da81670f96f9bp-47 },
+ { 0x1.ffffffffffff7p-1, 0x1.b24a16b4d09aap-47 },
+ { 0x1.ffffffffffff7p-1, 0x1.8d6eeb6efdbd6p-47 },
+ { 0x1.ffffffffffff8p-1, 0x1.6ba91ac734785p-47 },
+ { 0x1.ffffffffffff9p-1, 0x1.4cb7966770ab5p-47 },
+ { 0x1.ffffffffffff9p-1, 0x1.305e9721d0981p-47 },
+ { 0x1.ffffffffffffap-1, 0x1.1667311fff70ap-47 },
+ { 0x1.ffffffffffffbp-1, 0x1.fd3de10d62855p-48 },
+ { 0x1.ffffffffffffbp-1, 0x1.d1aefbcd48d0cp-48 },
+ { 0x1.ffffffffffffbp-1, 0x1.a9cc93c25aca9p-48 },
+ { 0x1.ffffffffffffcp-1, 0x1.85487ee3ea735p-48 },
+ { 0x1.ffffffffffffcp-1, 0x1.63daf8b4b1e0cp-48 },
+ { 0x1.ffffffffffffdp-1, 0x1.45421e69a6ca1p-48 },
+ { 0x1.ffffffffffffdp-1, 0x1.294175802d99ap-48 },
+ { 0x1.ffffffffffffdp-1, 0x1.0fa17bf41068fp-48 },
+ { 0x1.ffffffffffffdp-1, 0x1.f05e82aae2bb9p-49 },
+ { 0x1.ffffffffffffep-1, 0x1.c578101b29058p-49 },
+ { 0x1.ffffffffffffep-1, 0x1.9e39dc5dd2f7cp-49 },
+ { 0x1.ffffffffffffep-1, 0x1.7a553a728bbf2p-49 },
+ { 0x1.ffffffffffffep-1, 0x1.5982008db1304p-49 },
+ { 0x1.ffffffffffffep-1, 0x1.3b7e00422e51bp-49 },
+ { 0x1.ffffffffffffep-1, 0x1.200c898d9ee3ep-49 },
+ { 0x1.fffffffffffffp-1, 0x1.06f5f7eb65a56p-49 },
+ { 0x1.fffffffffffffp-1, 0x1.e00e9148a1d25p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.b623734024e92p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.8fd4e01891bf8p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.6cd44c7470d89p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.4cd9c04158cd7p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.2fa34bf5c8344p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.14f4890ff2461p-50 },
+ { 0x1.fffffffffffffp-1, 0x1.f92c49dfa4df5p-51 },
+ { 0x1.fffffffffffffp-1, 0x1.ccaaea71ab0dfp-51 },
+ { 0x1.fffffffffffffp-1, 0x1.a40829f001197p-51 },
+ { 0x1.0000000000000p+0, 0x1.7eef13b59e96cp-51 },
+ { 0x1.0000000000000p+0, 0x1.5d11e1a252bf5p-51 },
+ { 0x1.0000000000000p+0, 0x1.3e296303b2297p-51 },
+ { 0x1.0000000000000p+0, 0x1.21f47009f43cep-51 },
+ { 0x1.0000000000000p+0, 0x1.083768c5e4541p-51 },
+ { 0x1.0000000000000p+0, 0x1.e1777d831265ep-52 },
+ { 0x1.0000000000000p+0, 0x1.b69f10b0191b5p-52 },
+ { 0x1.0000000000000p+0, 0x1.8f8a3a05b5b52p-52 },
+ { 0x1.0000000000000p+0, 0x1.6be573c40c8e7p-52 },
+ { 0x1.0000000000000p+0, 0x1.4b645ba991fdbp-52 },
+ { 0x1.0000000000000p+0, 0x1.2dc119095729fp-52 },
+ },
+};
diff --git a/sysdeps/aarch64/fpu/erf_sve.c b/sysdeps/aarch64/fpu/erf_sve.c
new file mode 100644
index 0000000000..7d51417406
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erf_sve.c
@@ -0,0 +1,115 @@
+/* Double-precision vector (SVE) erf function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+
+static const struct data
+{
+ double third;
+ double tenth, two_over_five, two_over_fifteen;
+ double two_over_nine, two_over_fortyfive;
+ double max, shift;
+} data = {
+ .third = 0x1.5555555555556p-2, /* used to compute 2/3 and 1/6 too. */
+ .two_over_fifteen = 0x1.1111111111111p-3,
+ .tenth = -0x1.999999999999ap-4,
+ .two_over_five = -0x1.999999999999ap-2,
+ .two_over_nine = -0x1.c71c71c71c71cp-3,
+ .two_over_fortyfive = 0x1.6c16c16c16c17p-5,
+ .max = 5.9921875, /* 6 - 1/128. */
+ .shift = 0x1p45,
+};
+
+#define SignMask (0x8000000000000000)
+
+/* Double-precision implementation of vector erf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+ erf(x) ~ erf(r) + scale * d * [
+ + 1
+ - r d
+ + 1/3 (2 r^2 - 1) d^2
+ - 1/6 (r (2 r^2 - 3)) d^3
+ + 1/30 (4 r^4 - 12 r^2 + 3) d^4
+ - 1/90 (4 r^4 - 20 r^2 + 15) d^5
+ ]
+
+ Maximum measure error: 2.29 ULP
+ _ZGVsMxv_erf(-0x1.00003c924e5d1p-8) got -0x1.20dd59132ebadp-8
+ want -0x1.20dd59132ebafp-8. */
+svfloat64_t SV_NAME_D1 (erf) (svfloat64_t x, const svbool_t pg)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+ /* |x| >= 6.0 - 1/128. Opposite conditions except none of them catch NaNs so
+ they can be used in lookup and BSLs to yield the expected results. */
+ svbool_t a_ge_max = svacge (pg, x, dat->max);
+ svbool_t a_lt_max = svaclt (pg, x, dat->max);
+
+ /* Set r to multiple of 1/128 nearest to |x|. */
+ svfloat64_t a = svabs_x (pg, x);
+ svfloat64_t shift = sv_f64 (dat->shift);
+ svfloat64_t z = svadd_x (pg, a, shift);
+ svuint64_t i
+ = svsub_x (pg, svreinterpret_u64 (z), svreinterpret_u64 (shift));
+
+ /* Lookup without shortcut for small values but with predicate to avoid
+ segfault for large values and NaNs. */
+ svfloat64_t r = svsub_x (pg, z, shift);
+ svfloat64_t erfr = svld1_gather_index (a_lt_max, __sv_erf_data.erf, i);
+ svfloat64_t scale = svld1_gather_index (a_lt_max, __sv_erf_data.scale, i);
+
+ /* erf(x) ~ erf(r) + scale * d * poly (r, d). */
+ svfloat64_t d = svsub_x (pg, a, r);
+ svfloat64_t d2 = svmul_x (pg, d, d);
+ svfloat64_t r2 = svmul_x (pg, r, r);
+
+ /* poly (d, r) = 1 + p1(r) * d + p2(r) * d^2 + ... + p5(r) * d^5. */
+ svfloat64_t p1 = r;
+ svfloat64_t third = sv_f64 (dat->third);
+ svfloat64_t twothird = svmul_x (pg, third, 2.0);
+ svfloat64_t sixth = svmul_x (pg, third, 0.5);
+ svfloat64_t p2 = svmls_x (pg, third, r2, twothird);
+ svfloat64_t p3 = svmad_x (pg, r2, third, -0.5);
+ p3 = svmul_x (pg, r, p3);
+ svfloat64_t p4
+ = svmla_x (pg, sv_f64 (dat->two_over_five), r2, dat->two_over_fifteen);
+ p4 = svmls_x (pg, sv_f64 (dat->tenth), r2, p4);
+ svfloat64_t p5
+ = svmla_x (pg, sv_f64 (dat->two_over_nine), r2, dat->two_over_fortyfive);
+ p5 = svmla_x (pg, sixth, r2, p5);
+ p5 = svmul_x (pg, r, p5);
+
+ svfloat64_t p34 = svmla_x (pg, p3, d, p4);
+ svfloat64_t p12 = svmla_x (pg, p1, d, p2);
+ svfloat64_t y = svmla_x (pg, p34, d2, p5);
+ y = svmla_x (pg, p12, d2, y);
+
+ y = svmla_x (pg, erfr, scale, svmls_x (pg, d, d2, y));
+
+ /* Solves the |x| = inf and NaN cases. */
+ y = svsel (a_ge_max, sv_f64 (1.0), y);
+
+ /* Copy sign. */
+ svuint64_t ix = svreinterpret_u64 (x);
+ svuint64_t iy = svreinterpret_u64 (y);
+ svuint64_t sign = svand_x (pg, ix, SignMask);
+ return svreinterpret_f64 (svorr_x (pg, sign, iy));
+}
diff --git a/sysdeps/aarch64/fpu/erff_advsimd.c b/sysdeps/aarch64/fpu/erff_advsimd.c
new file mode 100644
index 0000000000..c44644a71c
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erff_advsimd.c
@@ -0,0 +1,123 @@
+/* Single-precision vector (Advanced SIMD) erf function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+
+static const struct data
+{
+ float32x4_t max, shift, third;
+#if WANT_SIMD_EXCEPT
+ float32x4_t tiny_bound, scale_minus_one;
+#endif
+} data = {
+ .max = V4 (3.9375), /* 4 - 8/128. */
+ .shift = V4 (0x1p16f),
+ .third = V4 (0x1.555556p-2f), /* 1/3. */
+#if WANT_SIMD_EXCEPT
+ .tiny_bound = V4 (0x1p-62f),
+ .scale_minus_one = V4 (0x1.06eba8p-3f), /* scale - 1.0. */
+#endif
+};
+
+#define AbsMask 0x7fffffff
+
+struct entry
+{
+ float32x4_t erf;
+ float32x4_t scale;
+};
+
+static inline struct entry
+lookup (uint32x4_t i)
+{
+ struct entry e;
+ float64_t t0 = *((float64_t *) (__erff_data.tab + i[0]));
+ float64_t t1 = *((float64_t *) (__erff_data.tab + i[1]));
+ float64_t t2 = *((float64_t *) (__erff_data.tab + i[2]));
+ float64_t t3 = *((float64_t *) (__erff_data.tab + i[3]));
+ float32x4_t e1 = vreinterpretq_f32_f64 ((float64x2_t){ t0, t1 });
+ float32x4_t e2 = vreinterpretq_f32_f64 ((float64x2_t){ t2, t3 });
+ e.erf = vuzp1q_f32 (e1, e2);
+ e.scale = vuzp2q_f32 (e1, e2);
+ return e;
+}
+
+/* Single-precision implementation of vector erf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erf(x) ~ erf(r) + scale * d * [1 - r * d - 1/3 * d^2]
+
+ Values of erf(r) and scale are read from lookup tables.
+ For |x| > 3.9375, erf(|x|) rounds to 1.0f.
+
+ Maximum error: 1.93 ULP
+ _ZGVnN4v_erff(0x1.c373e6p-9) got 0x1.fd686cp-9
+ want 0x1.fd6868p-9. */
+float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (erf) (float32x4_t x)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+#if WANT_SIMD_EXCEPT
+ /* |x| < 2^-62. */
+ uint32x4_t cmp = vcaltq_f32 (x, dat->tiny_bound);
+ float32x4_t xm = x;
+ /* If any lanes are special, mask them with 1 and retain a copy of x to allow
+ special case handler to fix special lanes later. This is only necessary if
+ fenv exceptions are to be triggered correctly. */
+ if (__glibc_unlikely (v_any_u32 (cmp)))
+ x = vbslq_f32 (cmp, v_f32 (1), x);
+#endif
+
+ float32x4_t a = vabsq_f32 (x);
+ uint32x4_t a_gt_max = vcgtq_f32 (a, dat->max);
+
+ /* Lookup erf(r) and scale(r) in tables, e.g. set erf(r) to 0 and scale to
+ 2/sqrt(pi), when x reduced to r = 0. */
+ float32x4_t shift = dat->shift;
+ float32x4_t z = vaddq_f32 (a, shift);
+
+ uint32x4_t i
+ = vsubq_u32 (vreinterpretq_u32_f32 (z), vreinterpretq_u32_f32 (shift));
+ i = vminq_u32 (i, v_u32 (512));
+ struct entry e = lookup (i);
+
+ float32x4_t r = vsubq_f32 (z, shift);
+
+ /* erf(x) ~ erf(r) + scale * d * (1 - r * d - 1/3 * d^2). */
+ float32x4_t d = vsubq_f32 (a, r);
+ float32x4_t d2 = vmulq_f32 (d, d);
+ float32x4_t y = vfmaq_f32 (r, dat->third, d);
+ y = vfmaq_f32 (e.erf, e.scale, vfmsq_f32 (d, d2, y));
+
+ /* Solves the |x| = inf case. */
+ y = vbslq_f32 (a_gt_max, v_f32 (1.0f), y);
+
+ /* Copy sign. */
+ y = vbslq_f32 (v_u32 (AbsMask), y, x);
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u32 (cmp)))
+ return vbslq_f32 (cmp, vfmaq_f32 (xm, dat->scale_minus_one, xm), y);
+#endif
+ return y;
+}
+libmvec_hidden_def (V_NAME_F1 (erf))
+HALF_WIDTH_ALIAS_F1 (erf)
diff --git a/sysdeps/aarch64/fpu/erff_data.c b/sysdeps/aarch64/fpu/erff_data.c
new file mode 100644
index 0000000000..9a32940915
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erff_data.c
@@ -0,0 +1,544 @@
+/* Table for Advanced SIMD erff approximation
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in erff.
+ For each possible rounded input r (multiples of 1/128), between
+ r = 0.0 and r = 4.0 (513 values):
+ - the first entry __erff_data.tab.erf contains the values of erf(r),
+ - the second entry __erff_data.tab.scale contains the values of
+ 2/sqrt(pi)*exp(-r^2). Note that indices 0 and 1 are never hit by the
+ algorithm, since lookup is performed only for x >= 1/64-1/512. */
+const struct erff_data __erff_data = {
+ .tab = { { 0x0.000000p+0, 0x1.20dd76p+0 },
+ { 0x1.20dbf4p-7, 0x1.20d8f2p+0 },
+ { 0x1.20d770p-6, 0x1.20cb68p+0 },
+ { 0x1.b137e0p-6, 0x1.20b4d8p+0 },
+ { 0x1.20c564p-5, 0x1.209546p+0 },
+ { 0x1.68e5d4p-5, 0x1.206cb4p+0 },
+ { 0x1.b0fafep-5, 0x1.203b26p+0 },
+ { 0x1.f902a8p-5, 0x1.2000a0p+0 },
+ { 0x1.207d48p-4, 0x1.1fbd28p+0 },
+ { 0x1.44703ep-4, 0x1.1f70c4p+0 },
+ { 0x1.68591ap-4, 0x1.1f1b7ap+0 },
+ { 0x1.8c36bep-4, 0x1.1ebd56p+0 },
+ { 0x1.b00812p-4, 0x1.1e565cp+0 },
+ { 0x1.d3cbf8p-4, 0x1.1de698p+0 },
+ { 0x1.f7815ap-4, 0x1.1d6e14p+0 },
+ { 0x1.0d9390p-3, 0x1.1cecdcp+0 },
+ { 0x1.1f5e1ap-3, 0x1.1c62fap+0 },
+ { 0x1.311fc2p-3, 0x1.1bd07cp+0 },
+ { 0x1.42d7fcp-3, 0x1.1b3572p+0 },
+ { 0x1.548642p-3, 0x1.1a91e6p+0 },
+ { 0x1.662a0cp-3, 0x1.19e5eap+0 },
+ { 0x1.77c2d2p-3, 0x1.19318cp+0 },
+ { 0x1.895010p-3, 0x1.1874dep+0 },
+ { 0x1.9ad142p-3, 0x1.17aff0p+0 },
+ { 0x1.ac45e4p-3, 0x1.16e2d8p+0 },
+ { 0x1.bdad72p-3, 0x1.160da4p+0 },
+ { 0x1.cf076ep-3, 0x1.153068p+0 },
+ { 0x1.e05354p-3, 0x1.144b3cp+0 },
+ { 0x1.f190aap-3, 0x1.135e30p+0 },
+ { 0x1.015f78p-2, 0x1.12695ep+0 },
+ { 0x1.09eed6p-2, 0x1.116cd8p+0 },
+ { 0x1.127632p-2, 0x1.1068bap+0 },
+ { 0x1.1af54ep-2, 0x1.0f5d16p+0 },
+ { 0x1.236bf0p-2, 0x1.0e4a08p+0 },
+ { 0x1.2bd9dcp-2, 0x1.0d2fa6p+0 },
+ { 0x1.343ed6p-2, 0x1.0c0e0ap+0 },
+ { 0x1.3c9aa8p-2, 0x1.0ae550p+0 },
+ { 0x1.44ed18p-2, 0x1.09b590p+0 },
+ { 0x1.4d35f0p-2, 0x1.087ee4p+0 },
+ { 0x1.5574f4p-2, 0x1.07416cp+0 },
+ { 0x1.5da9f4p-2, 0x1.05fd3ep+0 },
+ { 0x1.65d4b8p-2, 0x1.04b27cp+0 },
+ { 0x1.6df50ap-2, 0x1.036140p+0 },
+ { 0x1.760abap-2, 0x1.0209a6p+0 },
+ { 0x1.7e1594p-2, 0x1.00abd0p+0 },
+ { 0x1.861566p-2, 0x1.fe8fb0p-1 },
+ { 0x1.8e0a02p-2, 0x1.fbbbbep-1 },
+ { 0x1.95f336p-2, 0x1.f8dc0ap-1 },
+ { 0x1.9dd0d2p-2, 0x1.f5f0cep-1 },
+ { 0x1.a5a2acp-2, 0x1.f2fa4cp-1 },
+ { 0x1.ad6896p-2, 0x1.eff8c4p-1 },
+ { 0x1.b52264p-2, 0x1.ecec78p-1 },
+ { 0x1.bccfecp-2, 0x1.e9d5a8p-1 },
+ { 0x1.c47104p-2, 0x1.e6b498p-1 },
+ { 0x1.cc0584p-2, 0x1.e38988p-1 },
+ { 0x1.d38d44p-2, 0x1.e054bep-1 },
+ { 0x1.db081cp-2, 0x1.dd167cp-1 },
+ { 0x1.e275eap-2, 0x1.d9cf06p-1 },
+ { 0x1.e9d68ap-2, 0x1.d67ea2p-1 },
+ { 0x1.f129d4p-2, 0x1.d32592p-1 },
+ { 0x1.f86faap-2, 0x1.cfc41ep-1 },
+ { 0x1.ffa7eap-2, 0x1.cc5a8ap-1 },
+ { 0x1.03693ap-1, 0x1.c8e91cp-1 },
+ { 0x1.06f794p-1, 0x1.c5701ap-1 },
+ { 0x1.0a7ef6p-1, 0x1.c1efcap-1 },
+ { 0x1.0dff50p-1, 0x1.be6872p-1 },
+ { 0x1.117894p-1, 0x1.bada5ap-1 },
+ { 0x1.14eab4p-1, 0x1.b745c6p-1 },
+ { 0x1.1855a6p-1, 0x1.b3aafcp-1 },
+ { 0x1.1bb95cp-1, 0x1.b00a46p-1 },
+ { 0x1.1f15ccp-1, 0x1.ac63e8p-1 },
+ { 0x1.226ae8p-1, 0x1.a8b828p-1 },
+ { 0x1.25b8a8p-1, 0x1.a5074ep-1 },
+ { 0x1.28ff02p-1, 0x1.a1519ep-1 },
+ { 0x1.2c3decp-1, 0x1.9d9762p-1 },
+ { 0x1.2f755cp-1, 0x1.99d8dap-1 },
+ { 0x1.32a54cp-1, 0x1.961650p-1 },
+ { 0x1.35cdb4p-1, 0x1.925008p-1 },
+ { 0x1.38ee8ap-1, 0x1.8e8646p-1 },
+ { 0x1.3c07cap-1, 0x1.8ab950p-1 },
+ { 0x1.3f196ep-1, 0x1.86e96ap-1 },
+ { 0x1.42236ep-1, 0x1.8316d6p-1 },
+ { 0x1.4525c8p-1, 0x1.7f41dcp-1 },
+ { 0x1.482074p-1, 0x1.7b6abcp-1 },
+ { 0x1.4b1372p-1, 0x1.7791b8p-1 },
+ { 0x1.4dfebap-1, 0x1.73b714p-1 },
+ { 0x1.50e24cp-1, 0x1.6fdb12p-1 },
+ { 0x1.53be26p-1, 0x1.6bfdf0p-1 },
+ { 0x1.569244p-1, 0x1.681ff2p-1 },
+ { 0x1.595ea6p-1, 0x1.644156p-1 },
+ { 0x1.5c2348p-1, 0x1.60625cp-1 },
+ { 0x1.5ee02ep-1, 0x1.5c8342p-1 },
+ { 0x1.619556p-1, 0x1.58a446p-1 },
+ { 0x1.6442c0p-1, 0x1.54c5a6p-1 },
+ { 0x1.66e86ep-1, 0x1.50e79ep-1 },
+ { 0x1.69865ep-1, 0x1.4d0a68p-1 },
+ { 0x1.6c1c98p-1, 0x1.492e42p-1 },
+ { 0x1.6eab18p-1, 0x1.455366p-1 },
+ { 0x1.7131e6p-1, 0x1.417a0cp-1 },
+ { 0x1.73b102p-1, 0x1.3da26ep-1 },
+ { 0x1.762870p-1, 0x1.39ccc2p-1 },
+ { 0x1.789836p-1, 0x1.35f940p-1 },
+ { 0x1.7b0058p-1, 0x1.32281ep-1 },
+ { 0x1.7d60d8p-1, 0x1.2e5992p-1 },
+ { 0x1.7fb9c0p-1, 0x1.2a8dcep-1 },
+ { 0x1.820b12p-1, 0x1.26c508p-1 },
+ { 0x1.8454d6p-1, 0x1.22ff72p-1 },
+ { 0x1.869712p-1, 0x1.1f3d3cp-1 },
+ { 0x1.88d1cep-1, 0x1.1b7e98p-1 },
+ { 0x1.8b050ep-1, 0x1.17c3b6p-1 },
+ { 0x1.8d30dep-1, 0x1.140cc4p-1 },
+ { 0x1.8f5544p-1, 0x1.1059eep-1 },
+ { 0x1.91724ap-1, 0x1.0cab62p-1 },
+ { 0x1.9387f6p-1, 0x1.09014cp-1 },
+ { 0x1.959652p-1, 0x1.055bd6p-1 },
+ { 0x1.979d68p-1, 0x1.01bb2cp-1 },
+ { 0x1.999d42p-1, 0x1.fc3ee6p-2 },
+ { 0x1.9b95e8p-1, 0x1.f511aap-2 },
+ { 0x1.9d8768p-1, 0x1.edeeeep-2 },
+ { 0x1.9f71cap-1, 0x1.e6d700p-2 },
+ { 0x1.a1551ap-1, 0x1.dfca26p-2 },
+ { 0x1.a33162p-1, 0x1.d8c8aap-2 },
+ { 0x1.a506b0p-1, 0x1.d1d2d0p-2 },
+ { 0x1.a6d50cp-1, 0x1.cae8dap-2 },
+ { 0x1.a89c86p-1, 0x1.c40b08p-2 },
+ { 0x1.aa5d26p-1, 0x1.bd3998p-2 },
+ { 0x1.ac16fcp-1, 0x1.b674c8p-2 },
+ { 0x1.adca14p-1, 0x1.afbcd4p-2 },
+ { 0x1.af767ap-1, 0x1.a911f0p-2 },
+ { 0x1.b11c3cp-1, 0x1.a27456p-2 },
+ { 0x1.b2bb68p-1, 0x1.9be438p-2 },
+ { 0x1.b4540ap-1, 0x1.9561c8p-2 },
+ { 0x1.b5e630p-1, 0x1.8eed36p-2 },
+ { 0x1.b771e8p-1, 0x1.8886b2p-2 },
+ { 0x1.b8f742p-1, 0x1.822e66p-2 },
+ { 0x1.ba764ap-1, 0x1.7be47ap-2 },
+ { 0x1.bbef10p-1, 0x1.75a91ap-2 },
+ { 0x1.bd61a2p-1, 0x1.6f7c6ap-2 },
+ { 0x1.bece0ep-1, 0x1.695e8cp-2 },
+ { 0x1.c03464p-1, 0x1.634fa6p-2 },
+ { 0x1.c194b2p-1, 0x1.5d4fd4p-2 },
+ { 0x1.c2ef08p-1, 0x1.575f34p-2 },
+ { 0x1.c44376p-1, 0x1.517de6p-2 },
+ { 0x1.c5920ap-1, 0x1.4bac00p-2 },
+ { 0x1.c6dad2p-1, 0x1.45e99cp-2 },
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+ { 0x1.ffffe4p-1, 0x1.94219cp-18 },
+ { 0x1.ffffe6p-1, 0x1.7eb1a2p-18 },
+ { 0x1.ffffe8p-1, 0x1.6a5972p-18 },
+ { 0x1.ffffe8p-1, 0x1.570b6ap-18 },
+ { 0x1.ffffeap-1, 0x1.44ba86p-18 },
+ { 0x1.ffffeap-1, 0x1.335a62p-18 },
+ { 0x1.ffffecp-1, 0x1.22df2ap-18 },
+ { 0x1.ffffeep-1, 0x1.133d96p-18 },
+ { 0x1.ffffeep-1, 0x1.046aeap-18 },
+ { 0x1.fffff0p-1, 0x1.ecb9d0p-19 },
+ { 0x1.fffff0p-1, 0x1.d21398p-19 },
+ { 0x1.fffff2p-1, 0x1.b8d094p-19 },
+ { 0x1.fffff2p-1, 0x1.a0df10p-19 },
+ { 0x1.fffff2p-1, 0x1.8a2e26p-19 },
+ { 0x1.fffff4p-1, 0x1.74adc8p-19 },
+ { 0x1.fffff4p-1, 0x1.604ea8p-19 },
+ { 0x1.fffff4p-1, 0x1.4d0232p-19 },
+ { 0x1.fffff6p-1, 0x1.3aba86p-19 },
+ { 0x1.fffff6p-1, 0x1.296a70p-19 },
+ { 0x1.fffff6p-1, 0x1.190562p-19 },
+ { 0x1.fffff8p-1, 0x1.097f62p-19 },
+ { 0x1.fffff8p-1, 0x1.f59a20p-20 },
+ { 0x1.fffff8p-1, 0x1.d9c736p-20 },
+ { 0x1.fffff8p-1, 0x1.bf716cp-20 },
+ { 0x1.fffffap-1, 0x1.a6852cp-20 },
+ { 0x1.fffffap-1, 0x1.8eefd8p-20 },
+ { 0x1.fffffap-1, 0x1.789fb8p-20 },
+ { 0x1.fffffap-1, 0x1.6383f8p-20 },
+ { 0x1.fffffap-1, 0x1.4f8c96p-20 },
+ { 0x1.fffffap-1, 0x1.3caa62p-20 },
+ { 0x1.fffffcp-1, 0x1.2acee2p-20 },
+ { 0x1.fffffcp-1, 0x1.19ec60p-20 },
+ { 0x1.fffffcp-1, 0x1.09f5d0p-20 },
+ { 0x1.fffffcp-1, 0x1.f5bd96p-21 },
+ { 0x1.fffffcp-1, 0x1.d9371ep-21 },
+ { 0x1.fffffcp-1, 0x1.be41dep-21 },
+ { 0x1.fffffcp-1, 0x1.a4c89ep-21 },
+ { 0x1.fffffcp-1, 0x1.8cb738p-21 },
+ { 0x1.fffffep-1, 0x1.75fa8ep-21 },
+ { 0x1.fffffep-1, 0x1.608078p-21 },
+ { 0x1.fffffep-1, 0x1.4c37c0p-21 },
+ { 0x1.fffffep-1, 0x1.39100ep-21 },
+ { 0x1.fffffep-1, 0x1.26f9e0p-21 },
+ { 0x1.fffffep-1, 0x1.15e682p-21 },
+ { 0x1.fffffep-1, 0x1.05c804p-21 },
+ { 0x1.fffffep-1, 0x1.ed2254p-22 },
+ { 0x1.fffffep-1, 0x1.d06ad6p-22 },
+ { 0x1.fffffep-1, 0x1.b551c8p-22 },
+ { 0x1.fffffep-1, 0x1.9bc0a0p-22 },
+ { 0x1.fffffep-1, 0x1.83a200p-22 },
+ { 0x1.fffffep-1, 0x1.6ce1aap-22 },
+ { 0x1.fffffep-1, 0x1.576c72p-22 },
+ { 0x1.fffffep-1, 0x1.43302cp-22 },
+ { 0x1.fffffep-1, 0x1.301ba2p-22 },
+ { 0x1.fffffep-1, 0x1.1e1e86p-22 },
+ { 0x1.fffffep-1, 0x1.0d2966p-22 },
+ { 0x1.000000p+0, 0x1.fa5b50p-23 },
+ { 0x1.000000p+0, 0x1.dc3ae4p-23 },
+ { 0x1.000000p+0, 0x1.bfd756p-23 },
+ { 0x1.000000p+0, 0x1.a517dap-23 },
+ { 0x1.000000p+0, 0x1.8be4f8p-23 },
+ { 0x1.000000p+0, 0x1.74287ep-23 },
+ { 0x1.000000p+0, 0x1.5dcd66p-23 },
+ { 0x1.000000p+0, 0x1.48bfd4p-23 },
+ { 0x1.000000p+0, 0x1.34ecf8p-23 },
+ { 0x1.000000p+0, 0x1.224310p-23 },
+ { 0x1.000000p+0, 0x1.10b148p-23 },
+ },
+};
diff --git a/sysdeps/aarch64/fpu/erff_sve.c b/sysdeps/aarch64/fpu/erff_sve.c
new file mode 100644
index 0000000000..38f00db9be
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erff_sve.c
@@ -0,0 +1,93 @@
+/* Single-precision vector (SVE) erf function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+
+static const struct data
+{
+ float min, max, scale, shift, third;
+} data = {
+ .min = 0x1.cp-7f, /* 1/64 - 1/512. */
+ .max = 3.9375, /* 4 - 8/128. */
+ .scale = 0x1.20dd76p+0f, /* 2/sqrt(pi). */
+ .shift = 0x1p16f,
+ .third = 0x1.555556p-2f, /* 1/3. */
+};
+
+#define SignMask (0x80000000)
+
+/* Single-precision implementation of vector erf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erf(x) ~ erf(r) + scale * d * [1 - r * d - 1/3 * d^2]
+
+ Values of erf(r) and scale are read from lookup tables.
+ For |x| < 0x1.cp-7, the algorithm sets r = 0, erf(r) = 0, and scale = 2 /
+ sqrt(pi), so it simply boils down to a Taylor series expansion near 0. For
+ |x| > 3.9375, erf(|x|) rounds to 1.0f.
+
+ Maximum error on each interval:
+ - [0, 0x1.cp-7]: 1.93 ULP
+ _ZGVsMxv_erff(0x1.c373e6p-9) got 0x1.fd686cp-9 want 0x1.fd6868p-9
+ - [0x1.cp-7, 4.0]: 1.26 ULP
+ _ZGVsMxv_erff(0x1.1d002ep+0) got 0x1.c4eb9ap-1 want 0x1.c4eb98p-1. */
+svfloat32_t SV_NAME_F1 (erf) (svfloat32_t x, const svbool_t pg)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+ /* |x| > 1/64 - 1/512. */
+ svbool_t a_gt_min = svacgt (pg, x, dat->min);
+
+ /* |x| >= 4.0 - 8/128. */
+ svbool_t a_ge_max = svacge (pg, x, dat->max);
+ svfloat32_t a = svabs_x (pg, x);
+
+ svfloat32_t shift = sv_f32 (dat->shift);
+ svfloat32_t z = svadd_x (pg, a, shift);
+ svuint32_t i
+ = svsub_x (pg, svreinterpret_u32 (z), svreinterpret_u32 (shift));
+
+ /* Saturate lookup index. */
+ i = svsel (a_ge_max, sv_u32 (512), i);
+
+ /* r and erf(r) set to 0 for |x| below min. */
+ svfloat32_t r = svsub_z (a_gt_min, z, shift);
+ svfloat32_t erfr = svld1_gather_index (a_gt_min, __sv_erff_data.erf, i);
+
+ /* scale set to 2/sqrt(pi) for |x| below min. */
+ svfloat32_t scale = svld1_gather_index (a_gt_min, __sv_erff_data.scale, i);
+ scale = svsel (a_gt_min, scale, sv_f32 (dat->scale));
+
+ /* erf(x) ~ erf(r) + scale * d * (1 - r * d + 1/3 * d^2). */
+ svfloat32_t d = svsub_x (pg, a, r);
+ svfloat32_t d2 = svmul_x (pg, d, d);
+ svfloat32_t y = svmla_x (pg, r, d, dat->third);
+ y = svmla_x (pg, erfr, scale, svmls_x (pg, d, d2, y));
+
+ /* Solves the |x| = inf case. */
+ y = svsel (a_ge_max, sv_f32 (1.0f), y);
+
+ /* Copy sign. */
+ svuint32_t ix = svreinterpret_u32 (x);
+ svuint32_t iy = svreinterpret_u32 (y);
+ svuint32_t sign = svand_x (pg, ix, SignMask);
+ return svreinterpret_f32 (svorr_x (pg, sign, iy));
+}
diff --git a/sysdeps/aarch64/fpu/sv_erf_data.c b/sysdeps/aarch64/fpu/sv_erf_data.c
new file mode 100644
index 0000000000..a53878f893
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_erf_data.c
@@ -0,0 +1,1570 @@
+/* Table for SVE erf approximation
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in vector erf.
+ For each possible rounded input r (multiples of 1/128), between
+ r = 0.0 and r = 6.0 (769 values):
+ - the first entry __erf_data.tab.erf contains the values of erf(r),
+ - the second entry __erf_data.tab.scale contains the values of
+ 2/sqrt(pi)*exp(-r^2). Note that indices 0 and 1 are never hit by the
+ algorithm, since lookup is performed only for x >= 1/64-1/512. */
+const struct sv_erf_data __sv_erf_data = {
+ .erf = { 0x0.0000000000000p+0,
+ 0x1.20dbf3deb1340p-7,
+ 0x1.20d77083f17a0p-6,
+ 0x1.b137e0cf584dcp-6,
+ 0x1.20c5645dd2538p-5,
+ 0x1.68e5d3bbc9526p-5,
+ 0x1.b0fafef135745p-5,
+ 0x1.f902a77bd3821p-5,
+ 0x1.207d480e90658p-4,
+ 0x1.44703e87e8593p-4,
+ 0x1.68591a1e83b5dp-4,
+ 0x1.8c36beb8a8d23p-4,
+ 0x1.b0081148a873ap-4,
+ 0x1.d3cbf7e70a4b3p-4,
+ 0x1.f78159ec8bb50p-4,
+ 0x1.0d939005f65e5p-3,
+ 0x1.1f5e1a35c3b89p-3,
+ 0x1.311fc15f56d14p-3,
+ 0x1.42d7fc2f64959p-3,
+ 0x1.548642321d7c6p-3,
+ 0x1.662a0bdf7a89fp-3,
+ 0x1.77c2d2a765f9ep-3,
+ 0x1.895010fdbdbfdp-3,
+ 0x1.9ad142662e14dp-3,
+ 0x1.ac45e37fe2526p-3,
+ 0x1.bdad72110a648p-3,
+ 0x1.cf076d1233237p-3,
+ 0x1.e05354b96ff36p-3,
+ 0x1.f190aa85540e2p-3,
+ 0x1.015f78a3dcf3dp-2,
+ 0x1.09eed6982b948p-2,
+ 0x1.127631eb8de32p-2,
+ 0x1.1af54e232d609p-2,
+ 0x1.236bef825d9a2p-2,
+ 0x1.2bd9db0f7827fp-2,
+ 0x1.343ed6989b7d9p-2,
+ 0x1.3c9aa8b84bedap-2,
+ 0x1.44ed18d9f6462p-2,
+ 0x1.4d35ef3e5372ep-2,
+ 0x1.5574f4ffac98ep-2,
+ 0x1.5da9f415ff23fp-2,
+ 0x1.65d4b75b00471p-2,
+ 0x1.6df50a8dff772p-2,
+ 0x1.760aba57a76bfp-2,
+ 0x1.7e15944d9d3e4p-2,
+ 0x1.861566f5fd3c0p-2,
+ 0x1.8e0a01cab516bp-2,
+ 0x1.95f3353cbb146p-2,
+ 0x1.9dd0d2b721f39p-2,
+ 0x1.a5a2aca209394p-2,
+ 0x1.ad68966569a87p-2,
+ 0x1.b522646bbda68p-2,
+ 0x1.bccfec24855b8p-2,
+ 0x1.c4710406a65fcp-2,
+ 0x1.cc058392a6d2dp-2,
+ 0x1.d38d4354c3bd0p-2,
+ 0x1.db081ce6e2a48p-2,
+ 0x1.e275eaf25e458p-2,
+ 0x1.e9d68931ae650p-2,
+ 0x1.f129d471eabb1p-2,
+ 0x1.f86faa9428f9dp-2,
+ 0x1.ffa7ea8eb5fd0p-2,
+ 0x1.03693a371519cp-1,
+ 0x1.06f794ab2cae7p-1,
+ 0x1.0a7ef5c18edd2p-1,
+ 0x1.0dff4f247f6c6p-1,
+ 0x1.1178930ada115p-1,
+ 0x1.14eab43841b55p-1,
+ 0x1.1855a5fd3dd50p-1,
+ 0x1.1bb95c3746199p-1,
+ 0x1.1f15cb50bc4dep-1,
+ 0x1.226ae840d4d70p-1,
+ 0x1.25b8a88b6dd7fp-1,
+ 0x1.28ff0240d52cdp-1,
+ 0x1.2c3debfd7d6c1p-1,
+ 0x1.2f755ce9a21f4p-1,
+ 0x1.32a54cb8db67bp-1,
+ 0x1.35cdb3a9a144dp-1,
+ 0x1.38ee8a84beb71p-1,
+ 0x1.3c07ca9cb4f9ep-1,
+ 0x1.3f196dcd0f135p-1,
+ 0x1.42236e79a5fa6p-1,
+ 0x1.4525c78dd5966p-1,
+ 0x1.4820747ba2dc2p-1,
+ 0x1.4b13713ad3513p-1,
+ 0x1.4dfeba47f63ccp-1,
+ 0x1.50e24ca35fd2cp-1,
+ 0x1.53be25d016a4fp-1,
+ 0x1.569243d2b3a9bp-1,
+ 0x1.595ea53035283p-1,
+ 0x1.5c2348ecc4dc3p-1,
+ 0x1.5ee02e8a71a53p-1,
+ 0x1.61955607dd15dp-1,
+ 0x1.6442bfdedd397p-1,
+ 0x1.66e86d0312e82p-1,
+ 0x1.69865ee075011p-1,
+ 0x1.6c1c9759d0e5fp-1,
+ 0x1.6eab18c74091bp-1,
+ 0x1.7131e5f496a5ap-1,
+ 0x1.73b1021fc0cb8p-1,
+ 0x1.762870f720c6fp-1,
+ 0x1.78983697dc96fp-1,
+ 0x1.7b00578c26037p-1,
+ 0x1.7d60d8c979f7bp-1,
+ 0x1.7fb9bfaed8078p-1,
+ 0x1.820b1202f27fbp-1,
+ 0x1.8454d5f25760dp-1,
+ 0x1.8697120d92a4ap-1,
+ 0x1.88d1cd474a2e0p-1,
+ 0x1.8b050ef253c37p-1,
+ 0x1.8d30debfc572ep-1,
+ 0x1.8f5544bd00c04p-1,
+ 0x1.91724951b8fc6p-1,
+ 0x1.9387f53df5238p-1,
+ 0x1.959651980da31p-1,
+ 0x1.979d67caa6631p-1,
+ 0x1.999d4192a5715p-1,
+ 0x1.9b95e8fd26abap-1,
+ 0x1.9d8768656cc42p-1,
+ 0x1.9f71ca72cffb6p-1,
+ 0x1.a1551a16aaeafp-1,
+ 0x1.a331628a45b92p-1,
+ 0x1.a506af4cc00f4p-1,
+ 0x1.a6d50c20fa293p-1,
+ 0x1.a89c850b7d54dp-1,
+ 0x1.aa5d265064366p-1,
+ 0x1.ac16fc7143263p-1,
+ 0x1.adca142b10f98p-1,
+ 0x1.af767a741088bp-1,
+ 0x1.b11c3c79bb424p-1,
+ 0x1.b2bb679ead19cp-1,
+ 0x1.b4540978921eep-1,
+ 0x1.b5e62fce16095p-1,
+ 0x1.b771e894d602ep-1,
+ 0x1.b8f741ef54f83p-1,
+ 0x1.ba764a2af2b78p-1,
+ 0x1.bbef0fbde6221p-1,
+ 0x1.bd61a1453ab44p-1,
+ 0x1.bece0d82d1a5cp-1,
+ 0x1.c034635b66e23p-1,
+ 0x1.c194b1d49a184p-1,
+ 0x1.c2ef0812fc1bdp-1,
+ 0x1.c443755820d64p-1,
+ 0x1.c5920900b5fd1p-1,
+ 0x1.c6dad2829ec62p-1,
+ 0x1.c81de16b14cefp-1,
+ 0x1.c95b455cce69dp-1,
+ 0x1.ca930e0e2a825p-1,
+ 0x1.cbc54b476248dp-1,
+ 0x1.ccf20ce0c0d27p-1,
+ 0x1.ce1962c0e0d8bp-1,
+ 0x1.cf3b5cdaf0c39p-1,
+ 0x1.d0580b2cfd249p-1,
+ 0x1.d16f7dbe41ca0p-1,
+ 0x1.d281c49d818d0p-1,
+ 0x1.d38eefdf64fddp-1,
+ 0x1.d4970f9ce00d9p-1,
+ 0x1.d59a33f19ed42p-1,
+ 0x1.d6986cfa798e7p-1,
+ 0x1.d791cad3eff01p-1,
+ 0x1.d8865d98abe01p-1,
+ 0x1.d97635600bb89p-1,
+ 0x1.da61623cb41e0p-1,
+ 0x1.db47f43b2980dp-1,
+ 0x1.dc29fb60715afp-1,
+ 0x1.dd0787a8bb39dp-1,
+ 0x1.dde0a90611a0dp-1,
+ 0x1.deb56f5f12d28p-1,
+ 0x1.df85ea8db188ep-1,
+ 0x1.e0522a5dfda73p-1,
+ 0x1.e11a3e8cf4eb8p-1,
+ 0x1.e1de36c75ba58p-1,
+ 0x1.e29e22a89d766p-1,
+ 0x1.e35a11b9b61cep-1,
+ 0x1.e4121370224ccp-1,
+ 0x1.e4c6372cd8927p-1,
+ 0x1.e5768c3b4a3fcp-1,
+ 0x1.e62321d06c5e0p-1,
+ 0x1.e6cc0709c8a0dp-1,
+ 0x1.e7714aec96534p-1,
+ 0x1.e812fc64db369p-1,
+ 0x1.e8b12a44944a8p-1,
+ 0x1.e94be342e6743p-1,
+ 0x1.e9e335fb56f87p-1,
+ 0x1.ea7730ed0bbb9p-1,
+ 0x1.eb07e27a133aap-1,
+ 0x1.eb9558e6b42cep-1,
+ 0x1.ec1fa258c4beap-1,
+ 0x1.eca6ccd709544p-1,
+ 0x1.ed2ae6489ac1ep-1,
+ 0x1.edabfc7453e63p-1,
+ 0x1.ee2a1d004692cp-1,
+ 0x1.eea5557137ae0p-1,
+ 0x1.ef1db32a2277cp-1,
+ 0x1.ef93436bc2daap-1,
+ 0x1.f006135426b26p-1,
+ 0x1.f0762fde45ee6p-1,
+ 0x1.f0e3a5e1a1788p-1,
+ 0x1.f14e8211e8c55p-1,
+ 0x1.f1b6d0fea5f4dp-1,
+ 0x1.f21c9f12f0677p-1,
+ 0x1.f27ff89525acfp-1,
+ 0x1.f2e0e9a6a8b09p-1,
+ 0x1.f33f7e43a706bp-1,
+ 0x1.f39bc242e43e6p-1,
+ 0x1.f3f5c1558b19ep-1,
+ 0x1.f44d870704911p-1,
+ 0x1.f4a31ebcd47dfp-1,
+ 0x1.f4f693b67bd77p-1,
+ 0x1.f547f10d60597p-1,
+ 0x1.f59741b4b97cfp-1,
+ 0x1.f5e4907982a07p-1,
+ 0x1.f62fe80272419p-1,
+ 0x1.f67952cff6282p-1,
+ 0x1.f6c0db3c34641p-1,
+ 0x1.f7068b7b10fd9p-1,
+ 0x1.f74a6d9a38383p-1,
+ 0x1.f78c8b812d498p-1,
+ 0x1.f7cceef15d631p-1,
+ 0x1.f80ba18636f07p-1,
+ 0x1.f848acb544e95p-1,
+ 0x1.f88419ce4e184p-1,
+ 0x1.f8bdf1fb78370p-1,
+ 0x1.f8f63e416ebffp-1,
+ 0x1.f92d077f8d56dp-1,
+ 0x1.f96256700da8ep-1,
+ 0x1.f99633a838a57p-1,
+ 0x1.f9c8a7989af0dp-1,
+ 0x1.f9f9ba8d3c733p-1,
+ 0x1.fa2974addae45p-1,
+ 0x1.fa57ddfe27376p-1,
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+ 0x1.5a329b7d30748p-14,
+ 0x1.49e17724f4d41p-14,
+ 0x1.3a4b60ba9aa4dp-14,
+ 0x1.2b6875310f785p-14,
+ 0x1.1d312098e9dbap-14,
+ 0x1.0f9e1b4dd36dfp-14,
+ 0x1.02a8673a94691p-14,
+ 0x1.ec929a665b449p-15,
+ 0x1.d4f4b4c8e09edp-15,
+ 0x1.be6abbb10a5aap-15,
+ 0x1.a8e8cc1fadef6p-15,
+ 0x1.94637d5bacfdbp-15,
+ 0x1.80cfdc72220cfp-15,
+ 0x1.6e2367dc27f95p-15,
+ 0x1.5c540b4936fd2p-15,
+ 0x1.4b581b8d170fcp-15,
+ 0x1.3b2652b06c2b2p-15,
+ 0x1.2bb5cc22e5db6p-15,
+ 0x1.1cfe010e2052dp-15,
+ 0x1.0ef6c4c84a0fep-15,
+ 0x1.01984165a5f36p-15,
+ 0x1.e9b5e8d00ce76p-16,
+ 0x1.d16f5716c6c1ap-16,
+ 0x1.ba4f035d60e02p-16,
+ 0x1.a447b7b03f045p-16,
+ 0x1.8f4ccca7fc90dp-16,
+ 0x1.7b5223dac7336p-16,
+ 0x1.684c227fcacefp-16,
+ 0x1.562fac4329b48p-16,
+ 0x1.44f21e49054f2p-16,
+ 0x1.34894a5e24657p-16,
+ 0x1.24eb7254ccf83p-16,
+ 0x1.160f438c70913p-16,
+ 0x1.07ebd2a2d2844p-16,
+ 0x1.f4f12e9ab070ap-17,
+ 0x1.db5ad0b27805cp-17,
+ 0x1.c304efa2c6f4ep-17,
+ 0x1.abe09e9144b5ep-17,
+ 0x1.95df988e76644p-17,
+ 0x1.80f439b4ee04bp-17,
+ 0x1.6d11788a69c64p-17,
+ 0x1.5a2adfa0b4bc4p-17,
+ 0x1.4834877429b8fp-17,
+ 0x1.37231085c7d9ap-17,
+ 0x1.26eb9daed6f7ep-17,
+ 0x1.1783ceac28910p-17,
+ 0x1.08e1badf0fcedp-17,
+ 0x1.f5f7d88472604p-18,
+ 0x1.db92b5212fb8dp-18,
+ 0x1.c282cd3957edap-18,
+ 0x1.aab7abace48dcp-18,
+ 0x1.94219bfcb4928p-18,
+ 0x1.7eb1a2075864dp-18,
+ 0x1.6a597219a93d9p-18,
+ 0x1.570b69502f313p-18,
+ 0x1.44ba864670882p-18,
+ 0x1.335a62115bce2p-18,
+ 0x1.22df298214423p-18,
+ 0x1.133d96ae7e0ddp-18,
+ 0x1.046aeabcfcdecp-18,
+ 0x1.ecb9cfe1d8642p-19,
+ 0x1.d21397ead99cbp-19,
+ 0x1.b8d094c86d374p-19,
+ 0x1.a0df0f0c626dcp-19,
+ 0x1.8a2e269750a39p-19,
+ 0x1.74adc8f4064d3p-19,
+ 0x1.604ea819f007cp-19,
+ 0x1.4d0231928c6f9p-19,
+ 0x1.3aba85fe22e1fp-19,
+ 0x1.296a70f414053p-19,
+ 0x1.1905613b3abf2p-19,
+ 0x1.097f6156f32c5p-19,
+ 0x1.f59a20caf6695p-20,
+ 0x1.d9c73698fb1dcp-20,
+ 0x1.bf716c6168baep-20,
+ 0x1.a6852c6b58392p-20,
+ 0x1.8eefd70594a88p-20,
+ 0x1.789fb715aae95p-20,
+ 0x1.6383f726a8e04p-20,
+ 0x1.4f8c96f26a26ap-20,
+ 0x1.3caa61607f920p-20,
+ 0x1.2acee2f5ecdb8p-20,
+ 0x1.19ec60b1242edp-20,
+ 0x1.09f5cf4dd2877p-20,
+ 0x1.f5bd95d8730d8p-21,
+ 0x1.d9371e2ff7c35p-21,
+ 0x1.be41de54d155ap-21,
+ 0x1.a4c89e08ef4f3p-21,
+ 0x1.8cb738399b12cp-21,
+ 0x1.75fa8dbc84becp-21,
+ 0x1.608078a70dcbcp-21,
+ 0x1.4c37c0394d094p-21,
+ 0x1.39100d5687bfep-21,
+ 0x1.26f9df8519bd6p-21,
+ 0x1.15e6827001f18p-21,
+ 0x1.05c803e4831c1p-21,
+ 0x1.ed22548cffd35p-22,
+ 0x1.d06ad6ecdf971p-22,
+ 0x1.b551c847fbc96p-22,
+ 0x1.9bc09f112b494p-22,
+ 0x1.83a1ff0aa239dp-22,
+ 0x1.6ce1aa3fd7bddp-22,
+ 0x1.576c72b514859p-22,
+ 0x1.43302cc4a0da8p-22,
+ 0x1.301ba221dc9bbp-22,
+ 0x1.1e1e857adc568p-22,
+ 0x1.0d2966b1746f7p-22,
+ 0x1.fa5b4f49cc6b2p-23,
+ 0x1.dc3ae30b55c16p-23,
+ 0x1.bfd7555a3bd68p-23,
+ 0x1.a517d9e61628ap-23,
+ 0x1.8be4f8f6c951fp-23,
+ 0x1.74287ded49339p-23,
+ 0x1.5dcd669f2cd34p-23,
+ 0x1.48bfd38302870p-23,
+ 0x1.34ecf8a3c124ap-23,
+ 0x1.22430f521cbcfp-23,
+ 0x1.10b1488aeb235p-23,
+ 0x1.0027c00a263a6p-23,
+ 0x1.e12ee004efc37p-24,
+ 0x1.c3e44ae32b16bp-24,
+ 0x1.a854ea14102a8p-24,
+ 0x1.8e6761569f45dp-24,
+ 0x1.7603bac345f65p-24,
+ 0x1.5f1353cdad001p-24,
+ 0x1.4980cb3c80949p-24,
+ 0x1.3537f00b6ad4dp-24,
+ 0x1.2225b12bffc68p-24,
+ 0x1.10380e1adb7e9p-24,
+ 0x1.febc107d5efaap-25,
+ 0x1.df0f2a0ee6946p-25,
+ 0x1.c14b2188bcee4p-25,
+ 0x1.a553644f7f07dp-25,
+ 0x1.8b0cfce0579dfp-25,
+ 0x1.725e7c5dd20f7p-25,
+ 0x1.5b2fe547a1340p-25,
+ 0x1.456a974e92e93p-25,
+ 0x1.30f93c3699078p-25,
+ 0x1.1dc7b5b978cf8p-25,
+ 0x1.0bc30c5d52f15p-25,
+ 0x1.f5b2be65a0c7fp-26,
+ 0x1.d5f3a8dea7357p-26,
+ 0x1.b82915b03515bp-26,
+ 0x1.9c3517e789488p-26,
+ 0x1.81fb7df06136ep-26,
+ 0x1.6961b8d641d06p-26,
+ 0x1.524ec4d916caep-26,
+ 0x1.3cab1343d18d1p-26,
+ 0x1.2860757487a01p-26,
+ 0x1.155a09065d4f7p-26,
+ 0x1.0384250e4c9fcp-26,
+ 0x1.e59890b926c78p-27,
+ 0x1.c642116a8a9e3p-27,
+ 0x1.a8e405e651ab6p-27,
+ 0x1.8d5f98114f872p-27,
+ 0x1.7397c5a66e307p-27,
+ 0x1.5b71456c5a4c4p-27,
+ 0x1.44d26de513197p-27,
+ 0x1.2fa31d6371537p-27,
+ 0x1.1bcca373b7b43p-27,
+ 0x1.0939ab853339fp-27,
+ 0x1.efac5187b2863p-28,
+ 0x1.cf1e86235d0e6p-28,
+ 0x1.b0a68a2128babp-28,
+ 0x1.9423165bc4444p-28,
+ 0x1.7974e743dea3cp-28,
+ 0x1.607e9eacd1050p-28,
+ 0x1.4924a74dec728p-28,
+ 0x1.334d19e0c2160p-28,
+ 0x1.1edfa3c5f5ccap-28,
+ 0x1.0bc56f1b54701p-28,
+ 0x1.f3d2185e047d9p-29,
+ 0x1.d26cb87945e87p-29,
+ 0x1.b334fac4b9f99p-29,
+ 0x1.96076f7918d1cp-29,
+ 0x1.7ac2d72fc2c63p-29,
+ 0x1.614801550319ep-29,
+ 0x1.4979ac8b28926p-29,
+ 0x1.333c68e2d0548p-29,
+ 0x1.1e767bce37dd7p-29,
+ 0x1.0b0fc5b6d05a0p-29,
+ 0x1.f1e3523b41d7dp-30,
+ 0x1.d00de6608effep-30,
+ 0x1.b0778b7b3301ap-30,
+ 0x1.92fb04ec0f6cfp-30,
+ 0x1.77756ec9f78fap-30,
+ 0x1.5dc61922d5a06p-30,
+ 0x1.45ce65699ff6dp-30,
+ 0x1.2f71a5f159970p-30,
+ 0x1.1a94ff571654fp-30,
+ 0x1.071f4bbea09ecp-30,
+ 0x1.e9f1ff8ddd774p-31,
+ 0x1.c818223a202c7p-31,
+ 0x1.a887bd2b4404dp-31,
+ 0x1.8b1a336c5eb6bp-31,
+ 0x1.6fab63324088ap-31,
+ 0x1.56197e30205bap-31,
+ 0x1.3e44e45301b92p-31,
+ 0x1.281000bfe4c3fp-31,
+ 0x1.135f28f2d50b4p-31,
+ 0x1.00187dded5975p-31,
+ 0x1.dc479de0ef001p-32,
+ 0x1.bad4fdad3caa1p-32,
+ 0x1.9baed3ed27ab8p-32,
+ 0x1.7ead9ce4285bbp-32,
+ 0x1.63ac6b4edc88ep-32,
+ 0x1.4a88be2a6390cp-32,
+ 0x1.332259185f1a0p-32,
+ 0x1.1d5b1f3793044p-32,
+ 0x1.0916f04b6e18bp-32,
+ 0x1.ec77101de6926p-33,
+ 0x1.c960bf23153e0p-33,
+ 0x1.a8bd20fc65ef7p-33,
+ 0x1.8a61745ec7d1dp-33,
+ 0x1.6e25d0e756261p-33,
+ 0x1.53e4f7d1666cbp-33,
+ 0x1.3b7c27a7ddb0ep-33,
+ 0x1.24caf2c32af14p-33,
+ 0x1.0fb3186804d0fp-33,
+ 0x1.f830c0bb41fd7p-34,
+ 0x1.d3c0f1a91c846p-34,
+ 0x1.b1e5acf351d87p-34,
+ 0x1.92712d259ce66p-34,
+ 0x1.7538c60a04476p-34,
+ 0x1.5a14b04b47879p-34,
+ 0x1.40dfd87456f4cp-34,
+ 0x1.2977b1172b9d5p-34,
+ 0x1.13bc07e891491p-34,
+ 0x1.ff1dbb4300811p-35,
+ 0x1.d9a880f306bd8p-35,
+ 0x1.b6e45220b55e0p-35,
+ 0x1.96a0b33f2c4dap-35,
+ 0x1.78b07e9e924acp-35,
+ 0x1.5ce9ab1670dd2p-35,
+ 0x1.4325167006bb0p-35,
+ 0x1.2b3e53538ff3fp-35,
+ 0x1.15137a7f44864p-35,
+ 0x1.0084ff125639dp-35,
+ 0x1.daeb0b7311ec7p-36,
+ 0x1.b7937d1c40c52p-36,
+ 0x1.96d082f59ab06p-36,
+ 0x1.7872d9fa10aadp-36,
+ 0x1.5c4e8e37bc7d0p-36,
+ 0x1.423ac0df49a40p-36,
+ 0x1.2a117230ad284p-36,
+ 0x1.13af4f04f9998p-36,
+ 0x1.fde703724e560p-37,
+ 0x1.d77f0c82e7641p-37,
+ 0x1.b3ee02611d7ddp-37,
+ 0x1.92ff33023d5bdp-37,
+ 0x1.7481a9e69f53fp-37,
+ 0x1.5847eda620959p-37,
+ 0x1.3e27c1fcc74bdp-37,
+ 0x1.25f9ee0b923dcp-37,
+ 0x1.0f9a0686531ffp-37,
+ 0x1.f5cc7718082afp-38,
+ 0x1.cf7e53d6a2ca5p-38,
+ 0x1.ac0f5f3229372p-38,
+ 0x1.8b498644847eap-38,
+ 0x1.6cfa9bcca59dcp-38,
+ 0x1.50f411d4fd2cdp-38,
+ 0x1.370ab8327af5ep-38,
+ 0x1.1f167f88c6b6ep-38,
+ 0x1.08f24085d4597p-38,
+ 0x1.e8f70e181d619p-39,
+ 0x1.c324c20e337dcp-39,
+ 0x1.a03261574b54ep-39,
+ 0x1.7fe903cdf5855p-39,
+ 0x1.6215c58da3450p-39,
+ 0x1.46897d4b69fc6p-39,
+ 0x1.2d1877d731b7bp-39,
+ 0x1.159a386b11517p-39,
+ 0x1.ffd27ae9393cep-40,
+ 0x1.d7c593130dd0bp-40,
+ 0x1.b2cd607c79bcfp-40,
+ 0x1.90ae4d3405651p-40,
+ 0x1.71312dd1759e2p-40,
+ 0x1.5422ef5d8949dp-40,
+ 0x1.39544b0ecc957p-40,
+ 0x1.20997f73e73ddp-40,
+ 0x1.09ca0eaacd277p-40,
+ 0x1.e9810295890ecp-41,
+ 0x1.c2b45b5aa4a1dp-41,
+ 0x1.9eee068fa7596p-41,
+ 0x1.7df2b399c10a8p-41,
+ 0x1.5f8b87a31bd85p-41,
+ 0x1.4385c96e9a2d9p-41,
+ 0x1.29b2933ef4cbcp-41,
+ 0x1.11e68a6378f8ap-41,
+ 0x1.f7f338086a86bp-42,
+ 0x1.cf8d7d9ce040ap-42,
+ 0x1.aa577251ae484p-42,
+ 0x1.8811d739efb5ep-42,
+ 0x1.68823e52970bep-42,
+ 0x1.4b72ae68e8b4cp-42,
+ 0x1.30b14dbe876bcp-42,
+ 0x1.181012ef86610p-42,
+ 0x1.01647ba798744p-42,
+ 0x1.d90e917701675p-43,
+ 0x1.b2a87e86d0c8ap-43,
+ 0x1.8f53dcb377293p-43,
+ 0x1.6ed2f2515e933p-43,
+ 0x1.50ecc9ed47f19p-43,
+ 0x1.356cd5ce7799ep-43,
+ 0x1.1c229a587ab78p-43,
+ 0x1.04e15ecc7f3f6p-43,
+ 0x1.deffc7e6a6017p-44,
+ 0x1.b7b040832f310p-44,
+ 0x1.938e021f36d76p-44,
+ 0x1.7258610b3b233p-44,
+ 0x1.53d3bfc82a909p-44,
+ 0x1.37c92babdc2fdp-44,
+ 0x1.1e06010120f6ap-44,
+ 0x1.065b9616170d4p-44,
+ 0x1.e13dd96b3753ap-45,
+ 0x1.b950d32467392p-45,
+ 0x1.94a72263259a5p-45,
+ 0x1.72fd93e036cdcp-45,
+ 0x1.54164576929abp-45,
+ 0x1.37b83c521fe96p-45,
+ 0x1.1daf033182e96p-45,
+ 0x1.05ca50205d26ap-45,
+ 0x1.dfbb6235639fap-46,
+ 0x1.b7807e294781fp-46,
+ 0x1.9298add70a734p-46,
+ 0x1.70beaf9c7ffb6p-46,
+ 0x1.51b2cd6709222p-46,
+ 0x1.353a6cf7f7fffp-46,
+ 0x1.1b1fa8cbe84a7p-46,
+ 0x1.0330f0fd69921p-46,
+ 0x1.da81670f96f9bp-47,
+ 0x1.b24a16b4d09aap-47,
+ 0x1.8d6eeb6efdbd6p-47,
+ 0x1.6ba91ac734785p-47,
+ 0x1.4cb7966770ab5p-47,
+ 0x1.305e9721d0981p-47,
+ 0x1.1667311fff70ap-47,
+ 0x1.fd3de10d62855p-48,
+ 0x1.d1aefbcd48d0cp-48,
+ 0x1.a9cc93c25aca9p-48,
+ 0x1.85487ee3ea735p-48,
+ 0x1.63daf8b4b1e0cp-48,
+ 0x1.45421e69a6ca1p-48,
+ 0x1.294175802d99ap-48,
+ 0x1.0fa17bf41068fp-48,
+ 0x1.f05e82aae2bb9p-49,
+ 0x1.c578101b29058p-49,
+ 0x1.9e39dc5dd2f7cp-49,
+ 0x1.7a553a728bbf2p-49,
+ 0x1.5982008db1304p-49,
+ 0x1.3b7e00422e51bp-49,
+ 0x1.200c898d9ee3ep-49,
+ 0x1.06f5f7eb65a56p-49,
+ 0x1.e00e9148a1d25p-50,
+ 0x1.b623734024e92p-50,
+ 0x1.8fd4e01891bf8p-50,
+ 0x1.6cd44c7470d89p-50,
+ 0x1.4cd9c04158cd7p-50,
+ 0x1.2fa34bf5c8344p-50,
+ 0x1.14f4890ff2461p-50,
+ 0x1.f92c49dfa4df5p-51,
+ 0x1.ccaaea71ab0dfp-51,
+ 0x1.a40829f001197p-51,
+ 0x1.7eef13b59e96cp-51,
+ 0x1.5d11e1a252bf5p-51,
+ 0x1.3e296303b2297p-51,
+ 0x1.21f47009f43cep-51,
+ 0x1.083768c5e4541p-51,
+ 0x1.e1777d831265ep-52,
+ 0x1.b69f10b0191b5p-52,
+ 0x1.8f8a3a05b5b52p-52,
+ 0x1.6be573c40c8e7p-52,
+ 0x1.4b645ba991fdbp-52,
+ 0x1.2dc119095729fp-52,
+ },
+};
diff --git a/sysdeps/aarch64/fpu/sv_erff_data.c b/sysdeps/aarch64/fpu/sv_erff_data.c
new file mode 100644
index 0000000000..6dcd72af69
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_erff_data.c
@@ -0,0 +1,1058 @@
+/* Table for SVE erff approximation
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in SVE erff.
+ For each possible rounded input r (multiples of 1/128), between
+ r = 0.0 and r = 4.0 (513 values):
+ - __erff_data.erf contains the values of erf(r),
+ - __erff_data.scale contains the values of 2/sqrt(pi)*exp(-r^2).
+ Note that indices 0 and 1 are never hit by the algorithm, since lookup is
+ performed only for x >= 1/64-1/512. */
+const struct sv_erff_data __sv_erff_data = {
+ .erf = { 0x0.000000p+0,
+ 0x1.20dbf4p-7,
+ 0x1.20d770p-6,
+ 0x1.b137e0p-6,
+ 0x1.20c564p-5,
+ 0x1.68e5d4p-5,
+ 0x1.b0fafep-5,
+ 0x1.f902a8p-5,
+ 0x1.207d48p-4,
+ 0x1.44703ep-4,
+ 0x1.68591ap-4,
+ 0x1.8c36bep-4,
+ 0x1.b00812p-4,
+ 0x1.d3cbf8p-4,
+ 0x1.f7815ap-4,
+ 0x1.0d9390p-3,
+ 0x1.1f5e1ap-3,
+ 0x1.311fc2p-3,
+ 0x1.42d7fcp-3,
+ 0x1.548642p-3,
+ 0x1.662a0cp-3,
+ 0x1.77c2d2p-3,
+ 0x1.895010p-3,
+ 0x1.9ad142p-3,
+ 0x1.ac45e4p-3,
+ 0x1.bdad72p-3,
+ 0x1.cf076ep-3,
+ 0x1.e05354p-3,
+ 0x1.f190aap-3,
+ 0x1.015f78p-2,
+ 0x1.09eed6p-2,
+ 0x1.127632p-2,
+ 0x1.1af54ep-2,
+ 0x1.236bf0p-2,
+ 0x1.2bd9dcp-2,
+ 0x1.343ed6p-2,
+ 0x1.3c9aa8p-2,
+ 0x1.44ed18p-2,
+ 0x1.4d35f0p-2,
+ 0x1.5574f4p-2,
+ 0x1.5da9f4p-2,
+ 0x1.65d4b8p-2,
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+ 0x1.22ff72p-1,
+ 0x1.1f3d3cp-1,
+ 0x1.1b7e98p-1,
+ 0x1.17c3b6p-1,
+ 0x1.140cc4p-1,
+ 0x1.1059eep-1,
+ 0x1.0cab62p-1,
+ 0x1.09014cp-1,
+ 0x1.055bd6p-1,
+ 0x1.01bb2cp-1,
+ 0x1.fc3ee6p-2,
+ 0x1.f511aap-2,
+ 0x1.edeeeep-2,
+ 0x1.e6d700p-2,
+ 0x1.dfca26p-2,
+ 0x1.d8c8aap-2,
+ 0x1.d1d2d0p-2,
+ 0x1.cae8dap-2,
+ 0x1.c40b08p-2,
+ 0x1.bd3998p-2,
+ 0x1.b674c8p-2,
+ 0x1.afbcd4p-2,
+ 0x1.a911f0p-2,
+ 0x1.a27456p-2,
+ 0x1.9be438p-2,
+ 0x1.9561c8p-2,
+ 0x1.8eed36p-2,
+ 0x1.8886b2p-2,
+ 0x1.822e66p-2,
+ 0x1.7be47ap-2,
+ 0x1.75a91ap-2,
+ 0x1.6f7c6ap-2,
+ 0x1.695e8cp-2,
+ 0x1.634fa6p-2,
+ 0x1.5d4fd4p-2,
+ 0x1.575f34p-2,
+ 0x1.517de6p-2,
+ 0x1.4bac00p-2,
+ 0x1.45e99cp-2,
+ 0x1.4036d0p-2,
+ 0x1.3a93b2p-2,
+ 0x1.350052p-2,
+ 0x1.2f7cc4p-2,
+ 0x1.2a0916p-2,
+ 0x1.24a554p-2,
+ 0x1.1f518ap-2,
+ 0x1.1a0dc6p-2,
+ 0x1.14da0ap-2,
+ 0x1.0fb662p-2,
+ 0x1.0aa2d0p-2,
+ 0x1.059f5ap-2,
+ 0x1.00ac00p-2,
+ 0x1.f79184p-3,
+ 0x1.edeb40p-3,
+ 0x1.e46530p-3,
+ 0x1.daff4ap-3,
+ 0x1.d1b982p-3,
+ 0x1.c893cep-3,
+ 0x1.bf8e1cp-3,
+ 0x1.b6a856p-3,
+ 0x1.ade26cp-3,
+ 0x1.a53c42p-3,
+ 0x1.9cb5bep-3,
+ 0x1.944ec2p-3,
+ 0x1.8c0732p-3,
+ 0x1.83deeap-3,
+ 0x1.7bd5c8p-3,
+ 0x1.73eba4p-3,
+ 0x1.6c2056p-3,
+ 0x1.6473b6p-3,
+ 0x1.5ce596p-3,
+ 0x1.5575c8p-3,
+ 0x1.4e241ep-3,
+ 0x1.46f066p-3,
+ 0x1.3fda6cp-3,
+ 0x1.38e1fap-3,
+ 0x1.3206dcp-3,
+ 0x1.2b48dap-3,
+ 0x1.24a7b8p-3,
+ 0x1.1e233ep-3,
+ 0x1.17bb2cp-3,
+ 0x1.116f48p-3,
+ 0x1.0b3f52p-3,
+ 0x1.052b0cp-3,
+ 0x1.fe6460p-4,
+ 0x1.f2a902p-4,
+ 0x1.e72372p-4,
+ 0x1.dbd32ap-4,
+ 0x1.d0b7a0p-4,
+ 0x1.c5d04ap-4,
+ 0x1.bb1c98p-4,
+ 0x1.b09bfcp-4,
+ 0x1.a64de6p-4,
+ 0x1.9c31c6p-4,
+ 0x1.92470ap-4,
+ 0x1.888d1ep-4,
+ 0x1.7f036cp-4,
+ 0x1.75a960p-4,
+ 0x1.6c7e64p-4,
+ 0x1.6381e2p-4,
+ 0x1.5ab342p-4,
+ 0x1.5211ecp-4,
+ 0x1.499d48p-4,
+ 0x1.4154bcp-4,
+ 0x1.3937b2p-4,
+ 0x1.31458ep-4,
+ 0x1.297dbap-4,
+ 0x1.21df9ap-4,
+ 0x1.1a6a96p-4,
+ 0x1.131e14p-4,
+ 0x1.0bf97ep-4,
+ 0x1.04fc3ap-4,
+ 0x1.fc4b5ep-5,
+ 0x1.eeea8cp-5,
+ 0x1.e1d4d0p-5,
+ 0x1.d508fap-5,
+ 0x1.c885e0p-5,
+ 0x1.bc4a54p-5,
+ 0x1.b05530p-5,
+ 0x1.a4a54ap-5,
+ 0x1.99397ap-5,
+ 0x1.8e109cp-5,
+ 0x1.83298ep-5,
+ 0x1.78832cp-5,
+ 0x1.6e1c58p-5,
+ 0x1.63f3f6p-5,
+ 0x1.5a08e8p-5,
+ 0x1.505a18p-5,
+ 0x1.46e66cp-5,
+ 0x1.3dacd2p-5,
+ 0x1.34ac36p-5,
+ 0x1.2be38cp-5,
+ 0x1.2351c2p-5,
+ 0x1.1af5d2p-5,
+ 0x1.12ceb4p-5,
+ 0x1.0adb60p-5,
+ 0x1.031ad6p-5,
+ 0x1.f7182ap-6,
+ 0x1.e85c44p-6,
+ 0x1.da0006p-6,
+ 0x1.cc0180p-6,
+ 0x1.be5ecep-6,
+ 0x1.b1160ap-6,
+ 0x1.a4255ap-6,
+ 0x1.978ae8p-6,
+ 0x1.8b44e6p-6,
+ 0x1.7f5188p-6,
+ 0x1.73af0cp-6,
+ 0x1.685bb6p-6,
+ 0x1.5d55ccp-6,
+ 0x1.529b9ep-6,
+ 0x1.482b84p-6,
+ 0x1.3e03d8p-6,
+ 0x1.3422fep-6,
+ 0x1.2a875cp-6,
+ 0x1.212f62p-6,
+ 0x1.181984p-6,
+ 0x1.0f443ep-6,
+ 0x1.06ae14p-6,
+ 0x1.fcab14p-7,
+ 0x1.ec7262p-7,
+ 0x1.dcaf36p-7,
+ 0x1.cd5ecap-7,
+ 0x1.be7e5ap-7,
+ 0x1.b00b38p-7,
+ 0x1.a202bep-7,
+ 0x1.94624ep-7,
+ 0x1.87275ep-7,
+ 0x1.7a4f6ap-7,
+ 0x1.6dd7fep-7,
+ 0x1.61beaep-7,
+ 0x1.56011cp-7,
+ 0x1.4a9cf6p-7,
+ 0x1.3f8ff6p-7,
+ 0x1.34d7dcp-7,
+ 0x1.2a727ap-7,
+ 0x1.205dacp-7,
+ 0x1.169756p-7,
+ 0x1.0d1d6ap-7,
+ 0x1.03ede2p-7,
+ 0x1.f60d8ap-8,
+ 0x1.e4cc4ap-8,
+ 0x1.d4143ap-8,
+ 0x1.c3e1a6p-8,
+ 0x1.b430ecp-8,
+ 0x1.a4fe84p-8,
+ 0x1.9646f4p-8,
+ 0x1.8806d8p-8,
+ 0x1.7a3adep-8,
+ 0x1.6cdfccp-8,
+ 0x1.5ff276p-8,
+ 0x1.536fc2p-8,
+ 0x1.4754acp-8,
+ 0x1.3b9e40p-8,
+ 0x1.30499cp-8,
+ 0x1.2553eep-8,
+ 0x1.1aba78p-8,
+ 0x1.107a8cp-8,
+ 0x1.06918cp-8,
+ 0x1.f9f9d0p-9,
+ 0x1.e77448p-9,
+ 0x1.d58da6p-9,
+ 0x1.c4412cp-9,
+ 0x1.b38a3ap-9,
+ 0x1.a36454p-9,
+ 0x1.93cb12p-9,
+ 0x1.84ba30p-9,
+ 0x1.762d84p-9,
+ 0x1.682100p-9,
+ 0x1.5a90b0p-9,
+ 0x1.4d78bcp-9,
+ 0x1.40d564p-9,
+ 0x1.34a306p-9,
+ 0x1.28de12p-9,
+ 0x1.1d8318p-9,
+ 0x1.128ebap-9,
+ 0x1.07fdb4p-9,
+ 0x1.fb99b8p-10,
+ 0x1.e7f232p-10,
+ 0x1.d4fed8p-10,
+ 0x1.c2b9d0p-10,
+ 0x1.b11d70p-10,
+ 0x1.a02436p-10,
+ 0x1.8fc8c8p-10,
+ 0x1.8005f0p-10,
+ 0x1.70d6a4p-10,
+ 0x1.6235fcp-10,
+ 0x1.541f34p-10,
+ 0x1.468daep-10,
+ 0x1.397ceep-10,
+ 0x1.2ce898p-10,
+ 0x1.20cc76p-10,
+ 0x1.15246ep-10,
+ 0x1.09ec86p-10,
+ 0x1.fe41cep-11,
+ 0x1.e97ba4p-11,
+ 0x1.d57f52p-11,
+ 0x1.c245d4p-11,
+ 0x1.afc85ep-11,
+ 0x1.9e0058p-11,
+ 0x1.8ce75ep-11,
+ 0x1.7c7744p-11,
+ 0x1.6caa0ep-11,
+ 0x1.5d79ecp-11,
+ 0x1.4ee142p-11,
+ 0x1.40daa4p-11,
+ 0x1.3360ccp-11,
+ 0x1.266ea8p-11,
+ 0x1.19ff46p-11,
+ 0x1.0e0de8p-11,
+ 0x1.0295f0p-11,
+ 0x1.ef25d4p-12,
+ 0x1.da0110p-12,
+ 0x1.c5b542p-12,
+ 0x1.b23a5ap-12,
+ 0x1.9f8894p-12,
+ 0x1.8d986ap-12,
+ 0x1.7c629ap-12,
+ 0x1.6be022p-12,
+ 0x1.5c0a38p-12,
+ 0x1.4cda54p-12,
+ 0x1.3e4a24p-12,
+ 0x1.305390p-12,
+ 0x1.22f0b4p-12,
+ 0x1.161be4p-12,
+ 0x1.09cfa4p-12,
+ 0x1.fc0d56p-13,
+ 0x1.e577bcp-13,
+ 0x1.cfd4a6p-13,
+ 0x1.bb1a96p-13,
+ 0x1.a74068p-13,
+ 0x1.943d4ap-13,
+ 0x1.8208bcp-13,
+ 0x1.709a8ep-13,
+ 0x1.5feadap-13,
+ 0x1.4ff208p-13,
+ 0x1.40a8c2p-13,
+ 0x1.3207fcp-13,
+ 0x1.2408eap-13,
+ 0x1.16a502p-13,
+ 0x1.09d5f8p-13,
+ 0x1.fb2b7ap-14,
+ 0x1.e3bcf4p-14,
+ 0x1.cd5528p-14,
+ 0x1.b7e946p-14,
+ 0x1.a36eecp-14,
+ 0x1.8fdc1cp-14,
+ 0x1.7d2738p-14,
+ 0x1.6b4702p-14,
+ 0x1.5a329cp-14,
+ 0x1.49e178p-14,
+ 0x1.3a4b60p-14,
+ 0x1.2b6876p-14,
+ 0x1.1d3120p-14,
+ 0x1.0f9e1cp-14,
+ 0x1.02a868p-14,
+ 0x1.ec929ap-15,
+ 0x1.d4f4b4p-15,
+ 0x1.be6abcp-15,
+ 0x1.a8e8ccp-15,
+ 0x1.94637ep-15,
+ 0x1.80cfdcp-15,
+ 0x1.6e2368p-15,
+ 0x1.5c540cp-15,
+ 0x1.4b581cp-15,
+ 0x1.3b2652p-15,
+ 0x1.2bb5ccp-15,
+ 0x1.1cfe02p-15,
+ 0x1.0ef6c4p-15,
+ 0x1.019842p-15,
+ 0x1.e9b5e8p-16,
+ 0x1.d16f58p-16,
+ 0x1.ba4f04p-16,
+ 0x1.a447b8p-16,
+ 0x1.8f4cccp-16,
+ 0x1.7b5224p-16,
+ 0x1.684c22p-16,
+ 0x1.562facp-16,
+ 0x1.44f21ep-16,
+ 0x1.34894ap-16,
+ 0x1.24eb72p-16,
+ 0x1.160f44p-16,
+ 0x1.07ebd2p-16,
+ 0x1.f4f12ep-17,
+ 0x1.db5ad0p-17,
+ 0x1.c304f0p-17,
+ 0x1.abe09ep-17,
+ 0x1.95df98p-17,
+ 0x1.80f43ap-17,
+ 0x1.6d1178p-17,
+ 0x1.5a2ae0p-17,
+ 0x1.483488p-17,
+ 0x1.372310p-17,
+ 0x1.26eb9ep-17,
+ 0x1.1783cep-17,
+ 0x1.08e1bap-17,
+ 0x1.f5f7d8p-18,
+ 0x1.db92b6p-18,
+ 0x1.c282cep-18,
+ 0x1.aab7acp-18,
+ 0x1.94219cp-18,
+ 0x1.7eb1a2p-18,
+ 0x1.6a5972p-18,
+ 0x1.570b6ap-18,
+ 0x1.44ba86p-18,
+ 0x1.335a62p-18,
+ 0x1.22df2ap-18,
+ 0x1.133d96p-18,
+ 0x1.046aeap-18,
+ 0x1.ecb9d0p-19,
+ 0x1.d21398p-19,
+ 0x1.b8d094p-19,
+ 0x1.a0df10p-19,
+ 0x1.8a2e26p-19,
+ 0x1.74adc8p-19,
+ 0x1.604ea8p-19,
+ 0x1.4d0232p-19,
+ 0x1.3aba86p-19,
+ 0x1.296a70p-19,
+ 0x1.190562p-19,
+ 0x1.097f62p-19,
+ 0x1.f59a20p-20,
+ 0x1.d9c736p-20,
+ 0x1.bf716cp-20,
+ 0x1.a6852cp-20,
+ 0x1.8eefd8p-20,
+ 0x1.789fb8p-20,
+ 0x1.6383f8p-20,
+ 0x1.4f8c96p-20,
+ 0x1.3caa62p-20,
+ 0x1.2acee2p-20,
+ 0x1.19ec60p-20,
+ 0x1.09f5d0p-20,
+ 0x1.f5bd96p-21,
+ 0x1.d9371ep-21,
+ 0x1.be41dep-21,
+ 0x1.a4c89ep-21,
+ 0x1.8cb738p-21,
+ 0x1.75fa8ep-21,
+ 0x1.608078p-21,
+ 0x1.4c37c0p-21,
+ 0x1.39100ep-21,
+ 0x1.26f9e0p-21,
+ 0x1.15e682p-21,
+ 0x1.05c804p-21,
+ 0x1.ed2254p-22,
+ 0x1.d06ad6p-22,
+ 0x1.b551c8p-22,
+ 0x1.9bc0a0p-22,
+ 0x1.83a200p-22,
+ 0x1.6ce1aap-22,
+ 0x1.576c72p-22,
+ 0x1.43302cp-22,
+ 0x1.301ba2p-22,
+ 0x1.1e1e86p-22,
+ 0x1.0d2966p-22,
+ 0x1.fa5b50p-23,
+ 0x1.dc3ae4p-23,
+ 0x1.bfd756p-23,
+ 0x1.a517dap-23,
+ 0x1.8be4f8p-23,
+ 0x1.74287ep-23,
+ 0x1.5dcd66p-23,
+ 0x1.48bfd4p-23,
+ 0x1.34ecf8p-23,
+ 0x1.224310p-23,
+ 0x1.10b148p-23,
+ },
+};
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index caac3f7ce4..41fdb92d7e 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
+VPCS_VECTOR_WRAPPER (erf_advsimd, _ZGVnN2v_erf)
VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp)
VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10)
VPCS_VECTOR_WRAPPER (exp2_advsimd, _ZGVnN2v_exp2)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 2e29cbe739..8e3d64da42 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin)
SVE_VECTOR_WRAPPER (atan_sve, _ZGVsMxv_atan)
SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos)
+SVE_VECTOR_WRAPPER (erf_sve, _ZGVsMxv_erf)
SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp)
SVE_VECTOR_WRAPPER (exp10_sve, _ZGVsMxv_exp10)
SVE_VECTOR_WRAPPER (exp2_sve, _ZGVsMxv_exp2)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index c8a3df4bcd..33ae92878f 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
+VPCS_VECTOR_WRAPPER (erff_advsimd, _ZGVnN4v_erff)
VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf)
VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f)
VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index 0bc247b90b..ac0464f196 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf)
SVE_VECTOR_WRAPPER (atanf_sve, _ZGVsMxv_atanf)
SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf)
+SVE_VECTOR_WRAPPER (erff_sve, _ZGVsMxv_erff)
SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf)
SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f)
SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f)
diff --git a/sysdeps/aarch64/fpu/vecmath_config.h b/sysdeps/aarch64/fpu/vecmath_config.h
index 62f71f57f3..409c0c9bd9 100644
--- a/sysdeps/aarch64/fpu/vecmath_config.h
+++ b/sysdeps/aarch64/fpu/vecmath_config.h
@@ -84,4 +84,32 @@ extern const struct v_log10_data
} table[1 << V_LOG10_TABLE_BITS];
} __v_log10_data attribute_hidden;
+extern const struct erff_data
+{
+ struct
+ {
+ float erf, scale;
+ } tab[513];
+} __erff_data attribute_hidden;
+
+extern const struct sv_erff_data
+{
+ float erf[513];
+ float scale[513];
+} __sv_erff_data attribute_hidden;
+
+extern const struct erf_data
+{
+ struct
+ {
+ double erf, scale;
+ } tab[769];
+} __erf_data attribute_hidden;
+
+extern const struct sv_erf_data
+{
+ double erf[769];
+ double scale[769];
+} __sv_erf_data attribute_hidden;
+
#endif
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index 1d52bf9ebf..ed4791e26a 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -957,11 +957,19 @@ double: 1
float: 1
ldouble: 1
+Function: "erf_advsimd":
+double: 1
+float: 2
+
Function: "erf_downward":
double: 1
float: 1
ldouble: 2
+Function: "erf_sve":
+double: 1
+float: 2
+
Function: "erf_towardzero":
double: 1
float: 1
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index 580952b4de..6193518fb0 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -73,3 +73,8 @@ GLIBC_2.39 _ZGVsMxv_tan F
GLIBC_2.39 _ZGVsMxv_tanf F
GLIBC_2.39 _ZGVsMxvv_atan2 F
GLIBC_2.39 _ZGVsMxvv_atan2f F
+GLIBC_2.40 _ZGVnN2v_erf F
+GLIBC_2.40 _ZGVnN2v_erff F
+GLIBC_2.40 _ZGVnN4v_erff F
+GLIBC_2.40 _ZGVsMxv_erf F
+GLIBC_2.40 _ZGVsMxv_erff F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/8] aarch64/fpu: Add vector variants of cosh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:38 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 3/8] aarch64/fpu: Add vector variants of acosh Joe Ramsay
` (6 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 4 +-
sysdeps/aarch64/fpu/Versions | 5 +
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
sysdeps/aarch64/fpu/cosh_advsimd.c | 108 +++++++++++++++++
sysdeps/aarch64/fpu/cosh_sve.c | 105 +++++++++++++++++
sysdeps/aarch64/fpu/coshf_advsimd.c | 84 +++++++++++++
sysdeps/aarch64/fpu/coshf_sve.c | 59 ++++++++++
sysdeps/aarch64/fpu/sv_expf_inline.h | 75 ++++++++++++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/fpu/v_exp_tail_data.c | 110 ++++++++++++++++++
sysdeps/aarch64/fpu/v_expf_inline.h | 71 +++++++++++
sysdeps/aarch64/fpu/vecmath_config.h | 2 +
sysdeps/aarch64/libm-test-ulps | 8 ++
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
18 files changed, 648 insertions(+), 1 deletion(-)
create mode 100644 sysdeps/aarch64/fpu/cosh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/cosh_sve.c
create mode 100644 sysdeps/aarch64/fpu/coshf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/coshf_sve.c
create mode 100644 sysdeps/aarch64/fpu/sv_expf_inline.h
create mode 100644 sysdeps/aarch64/fpu/v_exp_tail_data.c
create mode 100644 sysdeps/aarch64/fpu/v_expf_inline.h
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index 320b6ed43a..019c3a5188 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -3,6 +3,7 @@ libmvec-supported-funcs = acos \
atan \
atan2 \
cos \
+ cosh \
erf \
exp \
exp10 \
@@ -32,7 +33,8 @@ libmvec-support = $(addsuffix f_advsimd,$(float-advsimd-funcs)) \
erf_data \
erff_data \
sv_erf_data \
- sv_erff_data
+ sv_erff_data \
+ v_exp_tail_data
endif
sve-cflags = -march=armv8-a+sve
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index d7b1e87191..884b4b57f0 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -79,6 +79,11 @@ libmvec {
_ZGVsMxv_tan;
}
GLIBC_2.40 {
+ _ZGVnN2v_cosh;
+ _ZGVnN2v_coshf;
+ _ZGVnN4v_coshf;
+ _ZGVsMxv_cosh;
+ _ZGVsMxv_coshf;
_ZGVnN2v_erf;
_ZGVnN2v_erff;
_ZGVnN4v_erff;
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index d8d88de218..c63b2948d4 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -21,6 +21,7 @@ libmvec_hidden_proto (V_NAME_F1(acos));
libmvec_hidden_proto (V_NAME_F1(asin));
libmvec_hidden_proto (V_NAME_F1(atan));
libmvec_hidden_proto (V_NAME_F1(cos));
+libmvec_hidden_proto (V_NAME_F1(cosh));
libmvec_hidden_proto (V_NAME_F1(erf));
libmvec_hidden_proto (V_NAME_F1(exp10));
libmvec_hidden_proto (V_NAME_F1(exp2));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 71f53363a0..8ca5509870 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -49,6 +49,10 @@
# define __DECL_SIMD_cos __DECL_SIMD_aarch64
# undef __DECL_SIMD_cosf
# define __DECL_SIMD_cosf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_cosh
+# define __DECL_SIMD_cosh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_coshf
+# define __DECL_SIMD_coshf __DECL_SIMD_aarch64
# undef __DECL_SIMD_erf
# define __DECL_SIMD_erf __DECL_SIMD_aarch64
# undef __DECL_SIMD_erff
@@ -124,6 +128,7 @@ __vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_erff (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t);
@@ -141,6 +146,7 @@ __vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_erf (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t);
@@ -163,6 +169,7 @@ __sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_erff (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t);
@@ -180,6 +187,7 @@ __sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_erf (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/cosh_advsimd.c b/sysdeps/aarch64/fpu/cosh_advsimd.c
new file mode 100644
index 0000000000..ec7b59637e
--- /dev/null
+++ b/sysdeps/aarch64/fpu/cosh_advsimd.c
@@ -0,0 +1,108 @@
+/* Double-precision vector (AdvSIMD) cosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+
+static const struct data
+{
+ float64x2_t poly[3];
+ float64x2_t inv_ln2, ln2, shift, thres;
+ uint64x2_t index_mask, special_bound;
+} data = {
+ .poly = { V2 (0x1.fffffffffffd4p-2), V2 (0x1.5555571d6b68cp-3),
+ V2 (0x1.5555576a59599p-5), },
+
+ .inv_ln2 = V2 (0x1.71547652b82fep8), /* N/ln2. */
+ /* -ln2/N. */
+ .ln2 = {-0x1.62e42fefa39efp-9, -0x1.abc9e3b39803f3p-64},
+ .shift = V2 (0x1.8p+52),
+ .thres = V2 (704.0),
+
+ .index_mask = V2 (0xff),
+ /* 0x1.6p9, above which exp overflows. */
+ .special_bound = V2 (0x4086000000000000),
+};
+
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
+{
+ return v_call_f64 (cosh, x, y, special);
+}
+
+/* Helper for approximating exp(x). Copied from v_exp_tail, with no
+ special-case handling or tail. */
+static inline float64x2_t
+exp_inline (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ /* n = round(x/(ln2/N)). */
+ float64x2_t z = vfmaq_f64 (d->shift, x, d->inv_ln2);
+ uint64x2_t u = vreinterpretq_u64_f64 (z);
+ float64x2_t n = vsubq_f64 (z, d->shift);
+
+ /* r = x - n*ln2/N. */
+ float64x2_t r = vfmaq_laneq_f64 (x, n, d->ln2, 0);
+ r = vfmaq_laneq_f64 (r, n, d->ln2, 1);
+
+ uint64x2_t e = vshlq_n_u64 (u, 52 - V_EXP_TAIL_TABLE_BITS);
+ uint64x2_t i = vandq_u64 (u, d->index_mask);
+
+ /* y = tail + exp(r) - 1 ~= r + C1 r^2 + C2 r^3 + C3 r^4. */
+ float64x2_t y = vfmaq_f64 (d->poly[1], d->poly[2], r);
+ y = vfmaq_f64 (d->poly[0], y, r);
+ y = vmulq_f64 (vfmaq_f64 (v_f64 (1), y, r), r);
+
+ /* s = 2^(n/N). */
+ u = v_lookup_u64 (__v_exp_tail_data, i);
+ float64x2_t s = vreinterpretq_f64_u64 (vaddq_u64 (u, e));
+
+ return vfmaq_f64 (s, y, s);
+}
+
+/* Approximation for vector double-precision cosh(x) using exp_inline.
+ cosh(x) = (exp(x) + exp(-x)) / 2.
+ The greatest observed error is in the scalar fall-back region, so is the
+ same as the scalar routine, 1.93 ULP:
+ _ZGVnN2v_cosh (0x1.628af341989dap+9) got 0x1.fdf28623ef921p+1021
+ want 0x1.fdf28623ef923p+1021.
+
+ The greatest observed error in the non-special region is 1.54 ULP:
+ _ZGVnN2v_cosh (0x1.8e205b6ecacf7p+2) got 0x1.f711dcb0c77afp+7
+ want 0x1.f711dcb0c77b1p+7. */
+float64x2_t VPCS_ATTR V_NAME_D1 (cosh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float64x2_t ax = vabsq_f64 (x);
+ uint64x2_t special
+ = vcgtq_u64 (vreinterpretq_u64_f64 (ax), d->special_bound);
+
+ /* Up to the point that exp overflows, we can use it to calculate cosh by
+ exp(|x|) / 2 + 1 / (2 * exp(|x|)). */
+ float64x2_t t = exp_inline (ax);
+ float64x2_t half_t = vmulq_n_f64 (t, 0.5);
+ float64x2_t half_over_t = vdivq_f64 (v_f64 (0.5), t);
+
+ /* Fall back to scalar for any special cases. */
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (x, vaddq_f64 (half_t, half_over_t), special);
+
+ return vaddq_f64 (half_t, half_over_t);
+}
diff --git a/sysdeps/aarch64/fpu/cosh_sve.c b/sysdeps/aarch64/fpu/cosh_sve.c
new file mode 100644
index 0000000000..919f34604a
--- /dev/null
+++ b/sysdeps/aarch64/fpu/cosh_sve.c
@@ -0,0 +1,105 @@
+/* Double-precision vector (SVE) cosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+
+static const struct data
+{
+ float64_t poly[3];
+ float64_t inv_ln2, ln2_hi, ln2_lo, shift, thres;
+ uint64_t index_mask, special_bound;
+} data = {
+ .poly = { 0x1.fffffffffffd4p-2, 0x1.5555571d6b68cp-3,
+ 0x1.5555576a59599p-5, },
+
+ .inv_ln2 = 0x1.71547652b82fep8, /* N/ln2. */
+ /* -ln2/N. */
+ .ln2_hi = -0x1.62e42fefa39efp-9,
+ .ln2_lo = -0x1.abc9e3b39803f3p-64,
+ .shift = 0x1.8p+52,
+ .thres = 704.0,
+
+ .index_mask = 0xff,
+ /* 0x1.6p9, above which exp overflows. */
+ .special_bound = 0x4086000000000000,
+};
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
+{
+ return sv_call_f64 (cosh, x, y, special);
+}
+
+/* Helper for approximating exp(x). Copied from sv_exp_tail, with no
+ special-case handling or tail. */
+static inline svfloat64_t
+exp_inline (svfloat64_t x, const svbool_t pg, const struct data *d)
+{
+ /* Calculate exp(x). */
+ svfloat64_t z = svmla_x (pg, sv_f64 (d->shift), x, d->inv_ln2);
+ svfloat64_t n = svsub_x (pg, z, d->shift);
+
+ svfloat64_t r = svmla_x (pg, x, n, d->ln2_hi);
+ r = svmla_x (pg, r, n, d->ln2_lo);
+
+ svuint64_t u = svreinterpret_u64 (z);
+ svuint64_t e = svlsl_x (pg, u, 52 - V_EXP_TAIL_TABLE_BITS);
+ svuint64_t i = svand_x (pg, u, d->index_mask);
+
+ svfloat64_t y = svmla_x (pg, sv_f64 (d->poly[1]), r, d->poly[2]);
+ y = svmla_x (pg, sv_f64 (d->poly[0]), r, y);
+ y = svmla_x (pg, sv_f64 (1.0), r, y);
+ y = svmul_x (pg, r, y);
+
+ /* s = 2^(n/N). */
+ u = svld1_gather_index (pg, __v_exp_tail_data, i);
+ svfloat64_t s = svreinterpret_f64 (svadd_x (pg, u, e));
+
+ return svmla_x (pg, s, s, y);
+}
+
+/* Approximation for SVE double-precision cosh(x) using exp_inline.
+ cosh(x) = (exp(x) + exp(-x)) / 2.
+ The greatest observed error is in the scalar fall-back region, so is the
+ same as the scalar routine, 1.93 ULP:
+ _ZGVsMxv_cosh (0x1.628ad45039d2fp+9) got 0x1.fd774e958236dp+1021
+ want 0x1.fd774e958236fp+1021.
+
+ The greatest observed error in the non-special region is 1.54 ULP:
+ _ZGVsMxv_cosh (0x1.ba5651dd4486bp+2) got 0x1.f5e2bb8d5c98fp+8
+ want 0x1.f5e2bb8d5c991p+8. */
+svfloat64_t SV_NAME_D1 (cosh) (svfloat64_t x, const svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svfloat64_t ax = svabs_x (pg, x);
+ svbool_t special = svcmpgt (pg, svreinterpret_u64 (ax), d->special_bound);
+
+ /* Up to the point that exp overflows, we can use it to calculate cosh by
+ exp(|x|) / 2 + 1 / (2 * exp(|x|)). */
+ svfloat64_t t = exp_inline (ax, pg, d);
+ svfloat64_t half_t = svmul_x (pg, t, 0.5);
+ svfloat64_t half_over_t = svdivr_x (pg, t, 0.5);
+
+ /* Fall back to scalar for any special cases. */
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svadd_x (pg, half_t, half_over_t), special);
+
+ return svadd_x (pg, half_t, half_over_t);
+}
diff --git a/sysdeps/aarch64/fpu/coshf_advsimd.c b/sysdeps/aarch64/fpu/coshf_advsimd.c
new file mode 100644
index 0000000000..c1ab4923b8
--- /dev/null
+++ b/sysdeps/aarch64/fpu/coshf_advsimd.c
@@ -0,0 +1,84 @@
+/* Single-precision vector (AdvSIMD) cosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_expf_inline.h"
+#include "v_math.h"
+
+static const struct data
+{
+ struct v_expf_data expf_consts;
+ uint32x4_t tiny_bound, special_bound;
+} data = {
+ .expf_consts = V_EXPF_DATA,
+ .tiny_bound = V4 (0x20000000), /* 0x1p-63: Round to 1 below this. */
+ /* 0x1.5a92d8p+6: expf overflows above this, so have to use special case. */
+ .special_bound = V4 (0x42ad496c),
+};
+
+#if !WANT_SIMD_EXCEPT
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
+{
+ return v_call_f32 (coshf, x, y, special);
+}
+#endif
+
+/* Single-precision vector cosh, using vector expf.
+ Maximum error is 2.38 ULP:
+ _ZGVnN4v_coshf (0x1.e8001ep+1) got 0x1.6a491ep+4
+ want 0x1.6a4922p+4. */
+float32x4_t VPCS_ATTR V_NAME_F1 (cosh) (float32x4_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float32x4_t ax = vabsq_f32 (x);
+ uint32x4_t iax = vreinterpretq_u32_f32 (ax);
+ uint32x4_t special = vcgeq_u32 (iax, d->special_bound);
+
+#if WANT_SIMD_EXCEPT
+ /* If fp exceptions are to be triggered correctly, fall back to the scalar
+ variant for all inputs if any input is a special value or above the bound
+ at which expf overflows. */
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return v_call_f32 (coshf, x, x, v_u32 (-1));
+
+ uint32x4_t tiny = vcleq_u32 (iax, d->tiny_bound);
+ /* If any input is tiny, avoid underflow exception by fixing tiny lanes of
+ input to 0, which will generate no exceptions. */
+ if (__glibc_unlikely (v_any_u32 (tiny)))
+ ax = v_zerofy_f32 (ax, tiny);
+#endif
+
+ /* Calculate cosh by exp(x) / 2 + exp(-x) / 2. */
+ float32x4_t t = v_expf_inline (ax, &d->expf_consts);
+ float32x4_t half_t = vmulq_n_f32 (t, 0.5);
+ float32x4_t half_over_t = vdivq_f32 (v_f32 (0.5), t);
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u32 (tiny)))
+ return vbslq_f32 (tiny, v_f32 (1), vaddq_f32 (half_t, half_over_t));
+#else
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return special_case (x, vaddq_f32 (half_t, half_over_t), special);
+#endif
+
+ return vaddq_f32 (half_t, half_over_t);
+}
+libmvec_hidden_def (V_NAME_F1 (cosh))
+HALF_WIDTH_ALIAS_F1 (cosh)
diff --git a/sysdeps/aarch64/fpu/coshf_sve.c b/sysdeps/aarch64/fpu/coshf_sve.c
new file mode 100644
index 0000000000..e5d8a299c6
--- /dev/null
+++ b/sysdeps/aarch64/fpu/coshf_sve.c
@@ -0,0 +1,59 @@
+/* Single-precision vector (SVE) cosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "sv_expf_inline.h"
+
+static const struct data
+{
+ struct sv_expf_data expf_consts;
+ uint32_t special_bound;
+} data = {
+ .expf_consts = SV_EXPF_DATA,
+ /* 0x1.5a92d8p+6: expf overflows above this, so have to use special case. */
+ .special_bound = 0x42ad496c,
+};
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t pg)
+{
+ return sv_call_f32 (coshf, x, y, pg);
+}
+
+/* Single-precision vector cosh, using vector expf.
+ Maximum error is 1.89 ULP:
+ _ZGVsMxv_coshf (-0x1.65898cp+6) got 0x1.f00aep+127
+ want 0x1.f00adcp+127. */
+svfloat32_t SV_NAME_F1 (cosh) (svfloat32_t x, svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svfloat32_t ax = svabs_x (pg, x);
+ svbool_t special = svcmpge (pg, svreinterpret_u32 (ax), d->special_bound);
+
+ /* Calculate cosh by exp(x) / 2 + exp(-x) / 2. */
+ svfloat32_t t = expf_inline (ax, pg, &d->expf_consts);
+ svfloat32_t half_t = svmul_x (pg, t, 0.5);
+ svfloat32_t half_over_t = svdivr_x (pg, t, 0.5);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svadd_x (pg, half_t, half_over_t), special);
+
+ return svadd_x (pg, half_t, half_over_t);
+}
diff --git a/sysdeps/aarch64/fpu/sv_expf_inline.h b/sysdeps/aarch64/fpu/sv_expf_inline.h
new file mode 100644
index 0000000000..23963b5f8e
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_expf_inline.h
@@ -0,0 +1,75 @@
+/* SVE helper for single-precision routines which depend on exp
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_SV_EXPF_INLINE_H
+#define AARCH64_FPU_SV_EXPF_INLINE_H
+
+#include "sv_math.h"
+
+struct sv_expf_data
+{
+ float poly[5];
+ float inv_ln2, ln2_hi, ln2_lo, shift;
+};
+
+/* Coefficients copied from the polynomial in AdvSIMD variant, reversed for
+ compatibility with polynomial helpers. Shift is 1.5*2^17 + 127. */
+#define SV_EXPF_DATA \
+ { \
+ .poly = { 0x1.ffffecp-1f, 0x1.fffdb6p-2f, 0x1.555e66p-3f, 0x1.573e2ep-5f, \
+ 0x1.0e4020p-7f }, \
+ \
+ .inv_ln2 = 0x1.715476p+0f, .ln2_hi = 0x1.62e4p-1f, \
+ .ln2_lo = 0x1.7f7d1cp-20f, .shift = 0x1.803f8p17f, \
+ }
+
+#define C(i) sv_f32 (d->poly[i])
+
+static inline svfloat32_t
+expf_inline (svfloat32_t x, const svbool_t pg, const struct sv_expf_data *d)
+{
+ /* exp(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)]
+ x = ln2*n + r, with r in [-ln2/2, ln2/2]. */
+
+ /* Load some constants in quad-word chunks to minimise memory access. */
+ svfloat32_t c4_invln2_and_ln2 = svld1rq (svptrue_b32 (), &d->poly[4]);
+
+ /* n = round(x/(ln2/N)). */
+ svfloat32_t z = svmla_lane (sv_f32 (d->shift), x, c4_invln2_and_ln2, 1);
+ svfloat32_t n = svsub_x (pg, z, d->shift);
+
+ /* r = x - n*ln2/N. */
+ svfloat32_t r = svmls_lane (x, n, c4_invln2_and_ln2, 2);
+ r = svmls_lane (r, n, c4_invln2_and_ln2, 3);
+
+ /* scale = 2^(n/N). */
+ svfloat32_t scale = svexpa (svreinterpret_u32_f32 (z));
+
+ /* y = exp(r) - 1 ~= r + C0 r^2 + C1 r^3 + C2 r^4 + C3 r^5 + C4 r^6. */
+ svfloat32_t p12 = svmla_x (pg, C (1), C (2), r);
+ svfloat32_t p34 = svmla_lane (C (3), r, c4_invln2_and_ln2, 0);
+ svfloat32_t r2 = svmul_f32_x (pg, r, r);
+ svfloat32_t p14 = svmla_x (pg, p12, p34, r2);
+ svfloat32_t p0 = svmul_f32_x (pg, r, C (0));
+ svfloat32_t poly = svmla_x (pg, p0, r2, p14);
+
+ return svmla_x (pg, scale, scale, poly);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index 41fdb92d7e..b37cb7d5e9 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
+VPCS_VECTOR_WRAPPER (cosh_advsimd, _ZGVnN2v_cosh)
VPCS_VECTOR_WRAPPER (erf_advsimd, _ZGVnN2v_erf)
VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp)
VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 8e3d64da42..011f07d2c1 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin)
SVE_VECTOR_WRAPPER (atan_sve, _ZGVsMxv_atan)
SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos)
+SVE_VECTOR_WRAPPER (cosh_sve, _ZGVsMxv_cosh)
SVE_VECTOR_WRAPPER (erf_sve, _ZGVsMxv_erf)
SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp)
SVE_VECTOR_WRAPPER (exp10_sve, _ZGVsMxv_exp10)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 33ae92878f..3545299143 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
+VPCS_VECTOR_WRAPPER (coshf_advsimd, _ZGVnN4v_coshf)
VPCS_VECTOR_WRAPPER (erff_advsimd, _ZGVnN4v_erff)
VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf)
VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index ac0464f196..bbc74ede88 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf)
SVE_VECTOR_WRAPPER (atanf_sve, _ZGVsMxv_atanf)
SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf)
+SVE_VECTOR_WRAPPER (coshf_sve, _ZGVsMxv_coshf)
SVE_VECTOR_WRAPPER (erff_sve, _ZGVsMxv_erff)
SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf)
SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f)
diff --git a/sysdeps/aarch64/fpu/v_exp_tail_data.c b/sysdeps/aarch64/fpu/v_exp_tail_data.c
new file mode 100644
index 0000000000..151e97c21b
--- /dev/null
+++ b/sysdeps/aarch64/fpu/v_exp_tail_data.c
@@ -0,0 +1,110 @@
+/* Lookup table for high-precision exp(x, tail) function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* 2^(j/N), j=0..N, N=2^8=256. */
+const uint64_t __v_exp_tail_data[] = {
+ 0x3ff0000000000000, 0x3feffb1afa5abcbf, 0x3feff63da9fb3335,
+ 0x3feff168143b0281, 0x3fefec9a3e778061, 0x3fefe7d42e11bbcc,
+ 0x3fefe315e86e7f85, 0x3fefde5f72f654b1, 0x3fefd9b0d3158574,
+ 0x3fefd50a0e3c1f89, 0x3fefd06b29ddf6de, 0x3fefcbd42b72a836,
+ 0x3fefc74518759bc8, 0x3fefc2bdf66607e0, 0x3fefbe3ecac6f383,
+ 0x3fefb9c79b1f3919, 0x3fefb5586cf9890f, 0x3fefb0f145e46c85,
+ 0x3fefac922b7247f7, 0x3fefa83b23395dec, 0x3fefa3ec32d3d1a2,
+ 0x3fef9fa55fdfa9c5, 0x3fef9b66affed31b, 0x3fef973028d7233e,
+ 0x3fef9301d0125b51, 0x3fef8edbab5e2ab6, 0x3fef8abdc06c31cc,
+ 0x3fef86a814f204ab, 0x3fef829aaea92de0, 0x3fef7e95934f312e,
+ 0x3fef7a98c8a58e51, 0x3fef76a45471c3c2, 0x3fef72b83c7d517b,
+ 0x3fef6ed48695bbc0, 0x3fef6af9388c8dea, 0x3fef672658375d2f,
+ 0x3fef635beb6fcb75, 0x3fef5f99f8138a1c, 0x3fef5be084045cd4,
+ 0x3fef582f95281c6b, 0x3fef54873168b9aa, 0x3fef50e75eb44027,
+ 0x3fef4d5022fcd91d, 0x3fef49c18438ce4d, 0x3fef463b88628cd6,
+ 0x3fef42be3578a819, 0x3fef3f49917ddc96, 0x3fef3bdda27912d1,
+ 0x3fef387a6e756238, 0x3fef351ffb82140a, 0x3fef31ce4fb2a63f,
+ 0x3fef2e85711ece75, 0x3fef2b4565e27cdd, 0x3fef280e341ddf29,
+ 0x3fef24dfe1f56381, 0x3fef21ba7591bb70, 0x3fef1e9df51fdee1,
+ 0x3fef1b8a66d10f13, 0x3fef187fd0dad990, 0x3fef157e39771b2f,
+ 0x3fef1285a6e4030b, 0x3fef0f961f641589, 0x3fef0cafa93e2f56,
+ 0x3fef09d24abd886b, 0x3fef06fe0a31b715, 0x3fef0432edeeb2fd,
+ 0x3fef0170fc4cd831, 0x3feefeb83ba8ea32, 0x3feefc08b26416ff,
+ 0x3feef96266e3fa2d, 0x3feef6c55f929ff1, 0x3feef431a2de883b,
+ 0x3feef1a7373aa9cb, 0x3feeef26231e754a, 0x3feeecae6d05d866,
+ 0x3feeea401b7140ef, 0x3feee7db34e59ff7, 0x3feee57fbfec6cf4,
+ 0x3feee32dc313a8e5, 0x3feee0e544ede173, 0x3feedea64c123422,
+ 0x3feedc70df1c5175, 0x3feeda4504ac801c, 0x3feed822c367a024,
+ 0x3feed60a21f72e2a, 0x3feed3fb2709468a, 0x3feed1f5d950a897,
+ 0x3feecffa3f84b9d4, 0x3feece086061892d, 0x3feecc2042a7d232,
+ 0x3feeca41ed1d0057, 0x3feec86d668b3237, 0x3feec6a2b5c13cd0,
+ 0x3feec4e1e192aed2, 0x3feec32af0d7d3de, 0x3feec17dea6db7d7,
+ 0x3feebfdad5362a27, 0x3feebe41b817c114, 0x3feebcb299fddd0d,
+ 0x3feebb2d81d8abff, 0x3feeb9b2769d2ca7, 0x3feeb8417f4531ee,
+ 0x3feeb6daa2cf6642, 0x3feeb57de83f4eef, 0x3feeb42b569d4f82,
+ 0x3feeb2e2f4f6ad27, 0x3feeb1a4ca5d920f, 0x3feeb070dde910d2,
+ 0x3feeaf4736b527da, 0x3feeae27dbe2c4cf, 0x3feead12d497c7fd,
+ 0x3feeac0827ff07cc, 0x3feeab07dd485429, 0x3feeaa11fba87a03,
+ 0x3feea9268a5946b7, 0x3feea84590998b93, 0x3feea76f15ad2148,
+ 0x3feea6a320dceb71, 0x3feea5e1b976dc09, 0x3feea52ae6cdf6f4,
+ 0x3feea47eb03a5585, 0x3feea3dd1d1929fd, 0x3feea34634ccc320,
+ 0x3feea2b9febc8fb7, 0x3feea23882552225, 0x3feea1c1c70833f6,
+ 0x3feea155d44ca973, 0x3feea0f4b19e9538, 0x3feea09e667f3bcd,
+ 0x3feea052fa75173e, 0x3feea012750bdabf, 0x3fee9fdcddd47645,
+ 0x3fee9fb23c651a2f, 0x3fee9f9298593ae5, 0x3fee9f7df9519484,
+ 0x3fee9f7466f42e87, 0x3fee9f75e8ec5f74, 0x3fee9f8286ead08a,
+ 0x3fee9f9a48a58174, 0x3fee9fbd35d7cbfd, 0x3fee9feb564267c9,
+ 0x3feea024b1ab6e09, 0x3feea0694fde5d3f, 0x3feea0b938ac1cf6,
+ 0x3feea11473eb0187, 0x3feea17b0976cfdb, 0x3feea1ed0130c132,
+ 0x3feea26a62ff86f0, 0x3feea2f336cf4e62, 0x3feea3878491c491,
+ 0x3feea427543e1a12, 0x3feea4d2add106d9, 0x3feea589994cce13,
+ 0x3feea64c1eb941f7, 0x3feea71a4623c7ad, 0x3feea7f4179f5b21,
+ 0x3feea8d99b4492ed, 0x3feea9cad931a436, 0x3feeaac7d98a6699,
+ 0x3feeabd0a478580f, 0x3feeace5422aa0db, 0x3feeae05bad61778,
+ 0x3feeaf3216b5448c, 0x3feeb06a5e0866d9, 0x3feeb1ae99157736,
+ 0x3feeb2fed0282c8a, 0x3feeb45b0b91ffc6, 0x3feeb5c353aa2fe2,
+ 0x3feeb737b0cdc5e5, 0x3feeb8b82b5f98e5, 0x3feeba44cbc8520f,
+ 0x3feebbdd9a7670b3, 0x3feebd829fde4e50, 0x3feebf33e47a22a2,
+ 0x3feec0f170ca07ba, 0x3feec2bb4d53fe0d, 0x3feec49182a3f090,
+ 0x3feec674194bb8d5, 0x3feec86319e32323, 0x3feeca5e8d07f29e,
+ 0x3feecc667b5de565, 0x3feece7aed8eb8bb, 0x3feed09bec4a2d33,
+ 0x3feed2c980460ad8, 0x3feed503b23e255d, 0x3feed74a8af46052,
+ 0x3feed99e1330b358, 0x3feedbfe53c12e59, 0x3feede6b5579fdbf,
+ 0x3feee0e521356eba, 0x3feee36bbfd3f37a, 0x3feee5ff3a3c2774,
+ 0x3feee89f995ad3ad, 0x3feeeb4ce622f2ff, 0x3feeee07298db666,
+ 0x3feef0ce6c9a8952, 0x3feef3a2b84f15fb, 0x3feef68415b749b1,
+ 0x3feef9728de5593a, 0x3feefc6e29f1c52a, 0x3feeff76f2fb5e47,
+ 0x3fef028cf22749e4, 0x3fef05b030a1064a, 0x3fef08e0b79a6f1f,
+ 0x3fef0c1e904bc1d2, 0x3fef0f69c3f3a207, 0x3fef12c25bd71e09,
+ 0x3fef16286141b33d, 0x3fef199bdd85529c, 0x3fef1d1cd9fa652c,
+ 0x3fef20ab5fffd07a, 0x3fef244778fafb22, 0x3fef27f12e57d14b,
+ 0x3fef2ba88988c933, 0x3fef2f6d9406e7b5, 0x3fef33405751c4db,
+ 0x3fef3720dcef9069, 0x3fef3b0f2e6d1675, 0x3fef3f0b555dc3fa,
+ 0x3fef43155b5bab74, 0x3fef472d4a07897c, 0x3fef4b532b08c968,
+ 0x3fef4f87080d89f2, 0x3fef53c8eacaa1d6, 0x3fef5818dcfba487,
+ 0x3fef5c76e862e6d3, 0x3fef60e316c98398, 0x3fef655d71ff6075,
+ 0x3fef69e603db3285, 0x3fef6e7cd63a8315, 0x3fef7321f301b460,
+ 0x3fef77d5641c0658, 0x3fef7c97337b9b5f, 0x3fef81676b197d17,
+ 0x3fef864614f5a129, 0x3fef8b333b16ee12, 0x3fef902ee78b3ff6,
+ 0x3fef953924676d76, 0x3fef9a51fbc74c83, 0x3fef9f7977cdb740,
+ 0x3fefa4afa2a490da, 0x3fefa9f4867cca6e, 0x3fefaf482d8e67f1,
+ 0x3fefb4aaa2188510, 0x3fefba1bee615a27, 0x3fefbf9c1cb6412a,
+ 0x3fefc52b376bba97, 0x3fefcac948dd7274, 0x3fefd0765b6e4540,
+ 0x3fefd632798844f8, 0x3fefdbfdad9cbe14, 0x3fefe1d802243c89,
+ 0x3fefe7c1819e90d8, 0x3fefedba3692d514, 0x3feff3c22b8f71f1,
+ 0x3feff9d96b2a23d9,
+};
diff --git a/sysdeps/aarch64/fpu/v_expf_inline.h b/sysdeps/aarch64/fpu/v_expf_inline.h
new file mode 100644
index 0000000000..a3b0e32f9e
--- /dev/null
+++ b/sysdeps/aarch64/fpu/v_expf_inline.h
@@ -0,0 +1,71 @@
+/* Helper for single-precision AdvSIMD routines which depend on exp
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_V_EXPF_INLINE_H
+#define AARCH64_FPU_V_EXPF_INLINE_H
+
+#include "v_math.h"
+
+struct v_expf_data
+{
+ float32x4_t poly[5];
+ float32x4_t shift, invln2_and_ln2;
+};
+
+/* maxerr: 1.45358 +0.5 ulp. */
+#define V_EXPF_DATA \
+ { \
+ .poly = { V4 (0x1.0e4020p-7f), V4 (0x1.573e2ep-5f), V4 (0x1.555e66p-3f), \
+ V4 (0x1.fffdb6p-2f), V4 (0x1.ffffecp-1f) }, \
+ .shift = V4 (0x1.8p23f), \
+ .invln2_and_ln2 = { 0x1.715476p+0f, 0x1.62e4p-1f, 0x1.7f7d1cp-20f, 0 }, \
+ }
+
+#define ExponentBias v_u32 (0x3f800000) /* asuint(1.0f). */
+#define C(i) d->poly[i]
+
+static inline float32x4_t
+v_expf_inline (float32x4_t x, const struct v_expf_data *d)
+{
+ /* Helper routine for calculating exp(x).
+ Copied from v_expf.c, with all special-case handling removed - the
+ calling routine should handle special values if required. */
+
+ /* exp(x) = 2^n (1 + poly(r)), with 1 + poly(r) in [1/sqrt(2),sqrt(2)]
+ x = ln2*n + r, with r in [-ln2/2, ln2/2]. */
+ float32x4_t n, r, z;
+ z = vfmaq_laneq_f32 (d->shift, x, d->invln2_and_ln2, 0);
+ n = vsubq_f32 (z, d->shift);
+ r = vfmsq_laneq_f32 (x, n, d->invln2_and_ln2, 1);
+ r = vfmsq_laneq_f32 (r, n, d->invln2_and_ln2, 2);
+ uint32x4_t e = vshlq_n_u32 (vreinterpretq_u32_f32 (z), 23);
+ float32x4_t scale = vreinterpretq_f32_u32 (vaddq_u32 (e, ExponentBias));
+
+ /* Custom order-4 Estrin avoids building high order monomial. */
+ float32x4_t r2 = vmulq_f32 (r, r);
+ float32x4_t p, q, poly;
+ p = vfmaq_f32 (C (1), C (0), r);
+ q = vfmaq_f32 (C (3), C (2), r);
+ q = vfmaq_f32 (q, p, r2);
+ p = vmulq_f32 (C (4), r);
+ poly = vfmaq_f32 (p, q, r2);
+ return vfmaq_f32 (scale, poly, scale);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/vecmath_config.h b/sysdeps/aarch64/fpu/vecmath_config.h
index 409c0c9bd9..3f0b5f4764 100644
--- a/sysdeps/aarch64/fpu/vecmath_config.h
+++ b/sysdeps/aarch64/fpu/vecmath_config.h
@@ -59,6 +59,8 @@ extern const struct v_log_data
} table[1 << V_LOG_TABLE_BITS];
} __v_log_data attribute_hidden;
+#define V_EXP_TAIL_TABLE_BITS 8
+extern const uint64_t __v_exp_tail_data[1 << V_EXP_TAIL_TABLE_BITS] attribute_hidden;
#define V_EXP_TABLE_BITS 7
extern const uint64_t __v_exp_data[1 << V_EXP_TABLE_BITS] attribute_hidden;
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index ed4791e26a..97f45236dd 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -701,11 +701,19 @@ double: 2
float: 2
ldouble: 2
+Function: "cosh_advsimd":
+double: 2
+float: 2
+
Function: "cosh_downward":
double: 3
float: 1
ldouble: 3
+Function: "cosh_sve":
+double: 2
+float: 2
+
Function: "cosh_towardzero":
double: 3
float: 1
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index 6193518fb0..f66da42c36 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -73,8 +73,13 @@ GLIBC_2.39 _ZGVsMxv_tan F
GLIBC_2.39 _ZGVsMxv_tanf F
GLIBC_2.39 _ZGVsMxvv_atan2 F
GLIBC_2.39 _ZGVsMxvv_atan2f F
+GLIBC_2.40 _ZGVnN2v_cosh F
+GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
+GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
+GLIBC_2.40 _ZGVsMxv_cosh F
+GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
GLIBC_2.40 _ZGVsMxv_erff F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/8] aarch64/fpu: Add vector variants of acosh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
2024-02-20 16:59 ` [PATCH 2/8] aarch64/fpu: Add vector variants of cosh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:42 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 4/8] aarch64/fpu: Add vector variants of asinh Joe Ramsay
` (5 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 1 +
sysdeps/aarch64/fpu/Versions | 5 +
sysdeps/aarch64/fpu/acosh_advsimd.c | 67 +++++++++++
sysdeps/aarch64/fpu/acosh_sve.c | 51 ++++++++
sysdeps/aarch64/fpu/acoshf_advsimd.c | 78 +++++++++++++
sysdeps/aarch64/fpu/acoshf_sve.c | 49 ++++++++
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
sysdeps/aarch64/fpu/sv_log1p_inline.h | 109 ++++++++++++++++++
sysdeps/aarch64/fpu/sv_log1pf_inline.h | 76 ++++++++++++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/fpu/v_log1p_inline.h | 103 +++++++++++++++++
sysdeps/aarch64/fpu/v_log1pf_inline.h | 78 +++++++++++++
sysdeps/aarch64/fpu/v_math.h | 10 ++
sysdeps/aarch64/libm-test-ulps | 8 ++
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
19 files changed, 653 insertions(+)
create mode 100644 sysdeps/aarch64/fpu/acosh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/acosh_sve.c
create mode 100644 sysdeps/aarch64/fpu/acoshf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/acoshf_sve.c
create mode 100644 sysdeps/aarch64/fpu/sv_log1p_inline.h
create mode 100644 sysdeps/aarch64/fpu/sv_log1pf_inline.h
create mode 100644 sysdeps/aarch64/fpu/v_log1p_inline.h
create mode 100644 sysdeps/aarch64/fpu/v_log1pf_inline.h
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index 019c3a5188..2e5bbb5a07 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -1,4 +1,5 @@
libmvec-supported-funcs = acos \
+ acosh \
asin \
atan \
atan2 \
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 884b4b57f0..60e1cdeace 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -79,6 +79,11 @@ libmvec {
_ZGVsMxv_tan;
}
GLIBC_2.40 {
+ _ZGVnN2v_acosh;
+ _ZGVnN2v_acoshf;
+ _ZGVnN4v_acoshf;
+ _ZGVsMxv_acosh;
+ _ZGVsMxv_acoshf;
_ZGVnN2v_cosh;
_ZGVnN2v_coshf;
_ZGVnN4v_coshf;
diff --git a/sysdeps/aarch64/fpu/acosh_advsimd.c b/sysdeps/aarch64/fpu/acosh_advsimd.c
new file mode 100644
index 0000000000..c88283cf11
--- /dev/null
+++ b/sysdeps/aarch64/fpu/acosh_advsimd.c
@@ -0,0 +1,67 @@
+/* Double-precision vector (Advanced SIMD) acosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WANT_V_LOG1P_K0_SHORTCUT 1
+#include "v_log1p_inline.h"
+
+const static struct data
+{
+ struct v_log1p_data log1p_consts;
+ uint64x2_t one, thresh;
+} data = {
+ .log1p_consts = V_LOG1P_CONSTANTS_TABLE,
+ .one = V2 (0x3ff0000000000000),
+ .thresh = V2 (0x1ff0000000000000) /* asuint64(0x1p511) - asuint64(1). */
+};
+
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x, float64x2_t y, uint64x2_t special,
+ const struct v_log1p_data *d)
+{
+ return v_call_f64 (acosh, x, log1p_inline (y, d), special);
+}
+
+/* Vector approximation for double-precision acosh, based on log1p.
+ The largest observed error is 3.02 ULP in the region where the
+ argument to log1p falls in the k=0 interval, i.e. x close to 1:
+ _ZGVnN2v_acosh(0x1.00798aaf80739p+0) got 0x1.f2d6d823bc9dfp-5
+ want 0x1.f2d6d823bc9e2p-5. */
+VPCS_ATTR float64x2_t V_NAME_D1 (acosh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+ uint64x2_t special
+ = vcgeq_u64 (vsubq_u64 (vreinterpretq_u64_f64 (x), d->one), d->thresh);
+ float64x2_t special_arg = x;
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u64 (special)))
+ x = vbslq_f64 (special, vreinterpretq_f64_u64 (d->one), x);
+#endif
+
+ float64x2_t xm1 = vsubq_f64 (x, v_f64 (1));
+ float64x2_t y;
+ y = vaddq_f64 (x, v_f64 (1));
+ y = vmulq_f64 (y, xm1);
+ y = vsqrtq_f64 (y);
+ y = vaddq_f64 (xm1, y);
+
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (special_arg, y, special, &d->log1p_consts);
+ return log1p_inline (y, &d->log1p_consts);
+}
diff --git a/sysdeps/aarch64/fpu/acosh_sve.c b/sysdeps/aarch64/fpu/acosh_sve.c
new file mode 100644
index 0000000000..3e4faaa5ca
--- /dev/null
+++ b/sysdeps/aarch64/fpu/acosh_sve.c
@@ -0,0 +1,51 @@
+/* Double-precision vector (SVE) acosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WANT_SV_LOG1P_K0_SHORTCUT 1
+#include "sv_log1p_inline.h"
+
+#define One (0x3ff0000000000000)
+#define Thres (0x1ff0000000000000) /* asuint64 (0x1p511) - One. */
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
+{
+ return sv_call_f64 (acosh, x, y, special);
+}
+
+/* SVE approximation for double-precision acosh, based on log1p.
+ The largest observed error is 3.19 ULP in the region where the
+ argument to log1p falls in the k=0 interval, i.e. x close to 1:
+ SV_NAME_D1 (acosh)(0x1.1e4388d4ca821p+0) got 0x1.ed23399f5137p-2
+ want 0x1.ed23399f51373p-2. */
+svfloat64_t SV_NAME_D1 (acosh) (svfloat64_t x, const svbool_t pg)
+{
+ /* (ix - One) >= (BigBound - One). */
+ svuint64_t ix = svreinterpret_u64 (x);
+ svbool_t special = svcmpge (pg, svsub_x (pg, ix, One), Thres);
+
+ svfloat64_t xm1 = svsub_x (pg, x, 1.0);
+ svfloat64_t u = svmul_x (pg, xm1, svadd_x (pg, x, 1.0));
+ svfloat64_t y = svadd_x (pg, xm1, svsqrt_x (pg, u));
+
+ /* Fall back to scalar routine for special lanes. */
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, sv_log1p_inline (y, pg), special);
+ return sv_log1p_inline (y, pg);
+}
diff --git a/sysdeps/aarch64/fpu/acoshf_advsimd.c b/sysdeps/aarch64/fpu/acoshf_advsimd.c
new file mode 100644
index 0000000000..8916dcbf40
--- /dev/null
+++ b/sysdeps/aarch64/fpu/acoshf_advsimd.c
@@ -0,0 +1,78 @@
+/* Single-precision vector (Advanced SIMD) acosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_log1pf_inline.h"
+
+#define SquareLim 0x1p64
+
+const static struct data
+{
+ struct v_log1pf_data log1pf_consts;
+ uint32x4_t one;
+ uint16x4_t thresh;
+} data = {
+ .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
+ .one = V4 (0x3f800000),
+ .thresh = V4 (0x2000) /* top(asuint(SquareLim) - asuint(1)). */
+};
+
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint16x4_t special,
+ const struct v_log1pf_data d)
+{
+ return v_call_f32 (acoshf, x, log1pf_inline (y, d), vmovl_u16 (special));
+}
+
+/* Vector approximation for single-precision acosh, based on log1p. Maximum
+ error depends on WANT_SIMD_EXCEPT. With SIMD fp exceptions enabled, it
+ is 2.78 ULP:
+ __v_acoshf(0x1.07887p+0) got 0x1.ef9e9cp-3
+ want 0x1.ef9ea2p-3.
+ With exceptions disabled, we can compute u with a shorter dependency chain,
+ which gives maximum error of 3.07 ULP:
+ __v_acoshf(0x1.01f83ep+0) got 0x1.fbc7fap-4
+ want 0x1.fbc7f4p-4. */
+
+VPCS_ATTR float32x4_t NOINLINE V_NAME_F1 (acosh) (float32x4_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+ uint32x4_t ix = vreinterpretq_u32_f32 (x);
+ uint16x4_t special = vcge_u16 (vsubhn_u32 (ix, d->one), d->thresh);
+
+#if WANT_SIMD_EXCEPT
+ /* Mask special lanes with 1 to side-step spurious invalid or overflow. Use
+ only xm1 to calculate u, as operating on x will trigger invalid for NaN.
+ Widening sign-extend special predicate in order to mask with it. */
+ uint32x4_t p
+ = vreinterpretq_u32_s32 (vmovl_s16 (vreinterpret_s16_u16 (special)));
+ float32x4_t xm1 = v_zerofy_f32 (vsubq_f32 (x, v_f32 (1)), p);
+ float32x4_t u = vfmaq_f32 (vaddq_f32 (xm1, xm1), xm1, xm1);
+#else
+ float32x4_t xm1 = vsubq_f32 (x, v_f32 (1));
+ float32x4_t u = vmulq_f32 (xm1, vaddq_f32 (x, v_f32 (1.0f)));
+#endif
+
+ float32x4_t y = vaddq_f32 (xm1, vsqrtq_f32 (u));
+
+ if (__glibc_unlikely (v_any_u16h (special)))
+ return special_case (x, y, special, d->log1pf_consts);
+ return log1pf_inline (y, d->log1pf_consts);
+}
+libmvec_hidden_def (V_NAME_F1 (acosh))
+HALF_WIDTH_ALIAS_F1 (acosh)
diff --git a/sysdeps/aarch64/fpu/acoshf_sve.c b/sysdeps/aarch64/fpu/acoshf_sve.c
new file mode 100644
index 0000000000..2110894e62
--- /dev/null
+++ b/sysdeps/aarch64/fpu/acoshf_sve.c
@@ -0,0 +1,49 @@
+/* Single-precision vector (SVE) acosh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define One 0x3f800000
+#define Thres 0x20000000 /* asuint(0x1p64) - One. */
+
+#include "sv_log1pf_inline.h"
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t special)
+{
+ return sv_call_f32 (acoshf, x, y, special);
+}
+
+/* Single-precision SVE acosh(x) routine. Implements the same algorithm as
+ vector acoshf and log1p.
+
+ Maximum error is 2.78 ULPs:
+ SV_NAME_F1 (acosh) (0x1.01e996p+0) got 0x1.f45b42p-4
+ want 0x1.f45b3cp-4. */
+svfloat32_t SV_NAME_F1 (acosh) (svfloat32_t x, const svbool_t pg)
+{
+ svuint32_t ix = svreinterpret_u32 (x);
+ svbool_t special = svcmpge (pg, svsub_x (pg, ix, One), Thres);
+
+ svfloat32_t xm1 = svsub_x (pg, x, 1.0f);
+ svfloat32_t u = svmul_x (pg, xm1, svadd_x (pg, x, 1.0f));
+ svfloat32_t y = sv_log1pf_inline (svadd_x (pg, xm1, svsqrt_x (pg, u)), pg);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, y, special);
+ return y;
+}
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index c63b2948d4..22fec4de77 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -18,6 +18,7 @@
<https://www.gnu.org/licenses/>. */
libmvec_hidden_proto (V_NAME_F1(acos));
+libmvec_hidden_proto (V_NAME_F1(acosh));
libmvec_hidden_proto (V_NAME_F1(asin));
libmvec_hidden_proto (V_NAME_F1(atan));
libmvec_hidden_proto (V_NAME_F1(cos));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 8ca5509870..841330956c 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -33,6 +33,10 @@
# define __DECL_SIMD_acos __DECL_SIMD_aarch64
# undef __DECL_SIMD_acosf
# define __DECL_SIMD_acosf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_acosh
+# define __DECL_SIMD_acosh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_acoshf
+# define __DECL_SIMD_acoshf __DECL_SIMD_aarch64
# undef __DECL_SIMD_asin
# define __DECL_SIMD_asin __DECL_SIMD_aarch64
# undef __DECL_SIMD_asinf
@@ -125,6 +129,7 @@ typedef __SVBool_t __sv_bool_t;
__vpcs __f32x4_t _ZGVnN4vv_atan2f (__f32x4_t, __f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_acoshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
@@ -143,6 +148,7 @@ __vpcs __f32x4_t _ZGVnN4v_tanf (__f32x4_t);
__vpcs __f64x2_t _ZGVnN2vv_atan2 (__f64x2_t, __f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_acosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
@@ -166,6 +172,7 @@ __vpcs __f64x2_t _ZGVnN2v_tan (__f64x2_t);
__sv_f32_t _ZGVsMxvv_atan2f (__sv_f32_t, __sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_acoshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
@@ -184,6 +191,7 @@ __sv_f32_t _ZGVsMxv_tanf (__sv_f32_t, __sv_bool_t);
__sv_f64_t _ZGVsMxvv_atan2 (__sv_f64_t, __sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_acosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/sv_log1p_inline.h b/sysdeps/aarch64/fpu/sv_log1p_inline.h
new file mode 100644
index 0000000000..da019674f9
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_log1p_inline.h
@@ -0,0 +1,109 @@
+/* Helper for double-precision SVE routines which depend on log1p
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_SV_LOG1P_INLINE_H
+#define AARCH64_FPU_SV_LOG1P_INLINE_H
+
+#include "sv_math.h"
+#include "poly_sve_f64.h"
+
+static const struct sv_log1p_data
+{
+ double poly[19], ln2[2];
+ uint64_t hf_rt2_top;
+ uint64_t one_m_hf_rt2_top;
+ uint32_t bottom_mask;
+ int64_t one_top;
+} sv_log1p_data = {
+ /* Coefficients generated using Remez, deg=20, in [sqrt(2)/2-1, sqrt(2)-1].
+ */
+ .poly = { -0x1.ffffffffffffbp-2, 0x1.55555555551a9p-2, -0x1.00000000008e3p-2,
+ 0x1.9999999a32797p-3, -0x1.555555552fecfp-3, 0x1.249248e071e5ap-3,
+ -0x1.ffffff8bf8482p-4, 0x1.c71c8f07da57ap-4, -0x1.9999ca4ccb617p-4,
+ 0x1.7459ad2e1dfa3p-4, -0x1.554d2680a3ff2p-4, 0x1.3b4c54d487455p-4,
+ -0x1.2548a9ffe80e6p-4, 0x1.0f389a24b2e07p-4, -0x1.eee4db15db335p-5,
+ 0x1.e95b494d4a5ddp-5, -0x1.15fdf07cb7c73p-4, 0x1.0310b70800fcfp-4,
+ -0x1.cfa7385bdb37ep-6 },
+ .ln2 = { 0x1.62e42fefa3800p-1, 0x1.ef35793c76730p-45 },
+ .hf_rt2_top = 0x3fe6a09e00000000,
+ .one_m_hf_rt2_top = 0x00095f6200000000,
+ .bottom_mask = 0xffffffff,
+ .one_top = 0x3ff
+};
+
+static inline svfloat64_t
+sv_log1p_inline (svfloat64_t x, const svbool_t pg)
+{
+ /* Helper for calculating log(x + 1). Adapted from v_log1p_inline.h, which
+ differs from v_log1p_2u5.c by:
+ - No special-case handling - this should be dealt with by the caller.
+ - Pairwise Horner polynomial evaluation for improved accuracy.
+ - Optionally simulate the shortcut for k=0, used in the scalar routine,
+ using svsel, for improved accuracy when the argument to log1p is close
+ to 0. This feature is enabled by defining WANT_SV_LOG1P_K0_SHORTCUT as 1
+ in the source of the caller before including this file.
+ See sv_log1p_2u1.c for details of the algorithm. */
+ const struct sv_log1p_data *d = ptr_barrier (&sv_log1p_data);
+ svfloat64_t m = svadd_x (pg, x, 1);
+ svuint64_t mi = svreinterpret_u64 (m);
+ svuint64_t u = svadd_x (pg, mi, d->one_m_hf_rt2_top);
+
+ svint64_t ki
+ = svsub_x (pg, svreinterpret_s64 (svlsr_x (pg, u, 52)), d->one_top);
+ svfloat64_t k = svcvt_f64_x (pg, ki);
+
+ /* Reduce x to f in [sqrt(2)/2, sqrt(2)]. */
+ svuint64_t utop
+ = svadd_x (pg, svand_x (pg, u, 0x000fffff00000000), d->hf_rt2_top);
+ svuint64_t u_red = svorr_x (pg, utop, svand_x (pg, mi, d->bottom_mask));
+ svfloat64_t f = svsub_x (pg, svreinterpret_f64 (u_red), 1);
+
+ /* Correction term c/m. */
+ svfloat64_t c = svsub_x (pg, x, svsub_x (pg, m, 1));
+ svfloat64_t cm;
+
+#ifndef WANT_SV_LOG1P_K0_SHORTCUT
+#error \
+ "Cannot use sv_log1p_inline.h without specifying whether you need the k0 shortcut for greater accuracy close to 0"
+#elif WANT_SV_LOG1P_K0_SHORTCUT
+ /* Shortcut if k is 0 - set correction term to 0 and f to x. The result is
+ that the approximation is solely the polynomial. */
+ svbool_t knot0 = svcmpne (pg, k, 0);
+ cm = svdiv_z (knot0, c, m);
+ if (__glibc_likely (!svptest_any (pg, knot0)))
+ {
+ f = svsel (knot0, f, x);
+ }
+#else
+ /* No shortcut. */
+ cm = svdiv_x (pg, c, m);
+#endif
+
+ /* Approximate log1p(f) on the reduced input using a polynomial. */
+ svfloat64_t f2 = svmul_x (pg, f, f);
+ svfloat64_t p = sv_pw_horner_18_f64_x (pg, f, f2, d->poly);
+
+ /* Assemble log1p(x) = k * log2 + log1p(f) + c/m. */
+ svfloat64_t ylo = svmla_x (pg, cm, k, d->ln2[0]);
+ svfloat64_t yhi = svmla_x (pg, f, k, d->ln2[1]);
+
+ return svmla_x (pg, svadd_x (pg, ylo, yhi), f2, p);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/sv_log1pf_inline.h b/sysdeps/aarch64/fpu/sv_log1pf_inline.h
new file mode 100644
index 0000000000..b94b2da055
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_log1pf_inline.h
@@ -0,0 +1,76 @@
+/* Helper for single-precision SVE routines which depend on log1p
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_SV_LOG1PF_INLINE_H
+#define AARCH64_FPU_SV_LOG1PF_INLINE_H
+
+#include "sv_math.h"
+#include "vecmath_config.h"
+#include "poly_sve_f32.h"
+
+static const struct sv_log1pf_data
+{
+ float32_t poly[9];
+ float32_t ln2;
+ float32_t scale_back;
+} sv_log1pf_data = {
+ /* Polynomial generated using FPMinimax in [-0.25, 0.5]. */
+ .poly = { -0x1p-1f, 0x1.5555aap-2f, -0x1.000038p-2f, 0x1.99675cp-3f,
+ -0x1.54ef78p-3f, 0x1.28a1f4p-3f, -0x1.0da91p-3f, 0x1.abcb6p-4f,
+ -0x1.6f0d5ep-5f },
+ .scale_back = 0x1.0p-23f,
+ .ln2 = 0x1.62e43p-1f,
+};
+
+static inline svfloat32_t
+eval_poly (svfloat32_t m, const float32_t *c, svbool_t pg)
+{
+ svfloat32_t p_12 = svmla_x (pg, sv_f32 (c[0]), m, sv_f32 (c[1]));
+ svfloat32_t m2 = svmul_x (pg, m, m);
+ svfloat32_t q = svmla_x (pg, m, m2, p_12);
+ svfloat32_t p = sv_pw_horner_6_f32_x (pg, m, m2, c + 2);
+ p = svmul_x (pg, m2, p);
+
+ return svmla_x (pg, q, m2, p);
+}
+
+static inline svfloat32_t
+sv_log1pf_inline (svfloat32_t x, svbool_t pg)
+{
+ const struct sv_log1pf_data *d = ptr_barrier (&sv_log1pf_data);
+
+ svfloat32_t m = svadd_x (pg, x, 1.0f);
+
+ svint32_t ks = svsub_x (pg, svreinterpret_s32 (m),
+ svreinterpret_s32 (svdup_f32 (0.75f)));
+ ks = svand_x (pg, ks, 0xff800000);
+ svuint32_t k = svreinterpret_u32 (ks);
+ svfloat32_t s = svreinterpret_f32 (
+ svsub_x (pg, svreinterpret_u32 (svdup_f32 (4.0f)), k));
+
+ svfloat32_t m_scale
+ = svreinterpret_f32 (svsub_x (pg, svreinterpret_u32 (x), k));
+ m_scale
+ = svadd_x (pg, m_scale, svmla_x (pg, sv_f32 (-1.0f), sv_f32 (0.25f), s));
+ svfloat32_t p = eval_poly (m_scale, d->poly, pg);
+ svfloat32_t scale_back = svmul_x (pg, svcvt_f32_x (pg, k), d->scale_back);
+ return svmla_x (pg, p, scale_back, d->ln2);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index b37cb7d5e9..f4ce1d7009 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -24,6 +24,7 @@
#define VEC_TYPE float64x2_t
VPCS_VECTOR_WRAPPER (acos_advsimd, _ZGVnN2v_acos)
+VPCS_VECTOR_WRAPPER (acosh_advsimd, _ZGVnN2v_acosh)
VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 011f07d2c1..0e973cc9d7 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -43,6 +43,7 @@
}
SVE_VECTOR_WRAPPER (acos_sve, _ZGVsMxv_acos)
+SVE_VECTOR_WRAPPER (acosh_sve, _ZGVsMxv_acosh)
SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin)
SVE_VECTOR_WRAPPER (atan_sve, _ZGVsMxv_atan)
SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 3545299143..0ce026b5ea 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -24,6 +24,7 @@
#define VEC_TYPE float32x4_t
VPCS_VECTOR_WRAPPER (acosf_advsimd, _ZGVnN4v_acosf)
+VPCS_VECTOR_WRAPPER (acoshf_advsimd, _ZGVnN4v_acoshf)
VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index bbc74ede88..398b7373e8 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -43,6 +43,7 @@
}
SVE_VECTOR_WRAPPER (acosf_sve, _ZGVsMxv_acosf)
+SVE_VECTOR_WRAPPER (acoshf_sve, _ZGVsMxv_acoshf)
SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf)
SVE_VECTOR_WRAPPER (atanf_sve, _ZGVsMxv_atanf)
SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
diff --git a/sysdeps/aarch64/fpu/v_log1p_inline.h b/sysdeps/aarch64/fpu/v_log1p_inline.h
new file mode 100644
index 0000000000..242e43b6ee
--- /dev/null
+++ b/sysdeps/aarch64/fpu/v_log1p_inline.h
@@ -0,0 +1,103 @@
+/* Helper for double-precision Advanced SIMD routines which depend on log1p
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_V_LOG1P_INLINE_H
+#define AARCH64_FPU_V_LOG1P_INLINE_H
+
+#include "v_math.h"
+#include "poly_advsimd_f64.h"
+
+struct v_log1p_data
+{
+ float64x2_t poly[19], ln2[2];
+ uint64x2_t hf_rt2_top, one_m_hf_rt2_top, umask;
+ int64x2_t one_top;
+};
+
+/* Coefficients generated using Remez, deg=20, in [sqrt(2)/2-1, sqrt(2)-1]. */
+#define V_LOG1P_CONSTANTS_TABLE \
+ { \
+ .poly = { V2 (-0x1.ffffffffffffbp-2), V2 (0x1.55555555551a9p-2), \
+ V2 (-0x1.00000000008e3p-2), V2 (0x1.9999999a32797p-3), \
+ V2 (-0x1.555555552fecfp-3), V2 (0x1.249248e071e5ap-3), \
+ V2 (-0x1.ffffff8bf8482p-4), V2 (0x1.c71c8f07da57ap-4), \
+ V2 (-0x1.9999ca4ccb617p-4), V2 (0x1.7459ad2e1dfa3p-4), \
+ V2 (-0x1.554d2680a3ff2p-4), V2 (0x1.3b4c54d487455p-4), \
+ V2 (-0x1.2548a9ffe80e6p-4), V2 (0x1.0f389a24b2e07p-4), \
+ V2 (-0x1.eee4db15db335p-5), V2 (0x1.e95b494d4a5ddp-5), \
+ V2 (-0x1.15fdf07cb7c73p-4), V2 (0x1.0310b70800fcfp-4), \
+ V2 (-0x1.cfa7385bdb37ep-6) }, \
+ .ln2 = { V2 (0x1.62e42fefa3800p-1), V2 (0x1.ef35793c76730p-45) }, \
+ .hf_rt2_top = V2 (0x3fe6a09e00000000), \
+ .one_m_hf_rt2_top = V2 (0x00095f6200000000), \
+ .umask = V2 (0x000fffff00000000), .one_top = V2 (0x3ff) \
+ }
+
+#define BottomMask v_u64 (0xffffffff)
+
+static inline float64x2_t
+log1p_inline (float64x2_t x, const struct v_log1p_data *d)
+{
+ /* Helper for calculating log(x + 1). Copied from v_log1p_2u5.c, with several
+ modifications:
+ - No special-case handling - this should be dealt with by the caller.
+ - Pairwise Horner polynomial evaluation for improved accuracy.
+ - Optionally simulate the shortcut for k=0, used in the scalar routine,
+ using v_sel, for improved accuracy when the argument to log1p is close to
+ 0. This feature is enabled by defining WANT_V_LOG1P_K0_SHORTCUT as 1 in
+ the source of the caller before including this file.
+ See v_log1pf_2u1.c for details of the algorithm. */
+ float64x2_t m = vaddq_f64 (x, v_f64 (1));
+ uint64x2_t mi = vreinterpretq_u64_f64 (m);
+ uint64x2_t u = vaddq_u64 (mi, d->one_m_hf_rt2_top);
+
+ int64x2_t ki
+ = vsubq_s64 (vreinterpretq_s64_u64 (vshrq_n_u64 (u, 52)), d->one_top);
+ float64x2_t k = vcvtq_f64_s64 (ki);
+
+ /* Reduce x to f in [sqrt(2)/2, sqrt(2)]. */
+ uint64x2_t utop = vaddq_u64 (vandq_u64 (u, d->umask), d->hf_rt2_top);
+ uint64x2_t u_red = vorrq_u64 (utop, vandq_u64 (mi, BottomMask));
+ float64x2_t f = vsubq_f64 (vreinterpretq_f64_u64 (u_red), v_f64 (1));
+
+ /* Correction term c/m. */
+ float64x2_t cm = vdivq_f64 (vsubq_f64 (x, vsubq_f64 (m, v_f64 (1))), m);
+
+#ifndef WANT_V_LOG1P_K0_SHORTCUT
+#error \
+ "Cannot use v_log1p_inline.h without specifying whether you need the k0 shortcut for greater accuracy close to 0"
+#elif WANT_V_LOG1P_K0_SHORTCUT
+ /* Shortcut if k is 0 - set correction term to 0 and f to x. The result is
+ that the approximation is solely the polynomial. */
+ uint64x2_t k0 = vceqzq_f64 (k);
+ cm = v_zerofy_f64 (cm, k0);
+ f = vbslq_f64 (k0, x, f);
+#endif
+
+ /* Approximate log1p(f) on the reduced input using a polynomial. */
+ float64x2_t f2 = vmulq_f64 (f, f);
+ float64x2_t p = v_pw_horner_18_f64 (f, f2, d->poly);
+
+ /* Assemble log1p(x) = k * log2 + log1p(f) + c/m. */
+ float64x2_t ylo = vfmaq_f64 (cm, k, d->ln2[1]);
+ float64x2_t yhi = vfmaq_f64 (f, k, d->ln2[0]);
+ return vfmaq_f64 (vaddq_f64 (ylo, yhi), f2, p);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/v_log1pf_inline.h b/sysdeps/aarch64/fpu/v_log1pf_inline.h
new file mode 100644
index 0000000000..643a6cdcfc
--- /dev/null
+++ b/sysdeps/aarch64/fpu/v_log1pf_inline.h
@@ -0,0 +1,78 @@
+/* Helper for single-precision Advanced SIMD routines which depend on log1p
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_V_LOG1PF_INLINE_H
+#define AARCH64_FPU_V_LOG1PF_INLINE_H
+
+#include "v_math.h"
+#include "poly_advsimd_f32.h"
+
+struct v_log1pf_data
+{
+ float32x4_t poly[8], ln2;
+ uint32x4_t four;
+ int32x4_t three_quarters;
+};
+
+/* Polynomial generated using FPMinimax in [-0.25, 0.5]. First two coefficients
+ (1, -0.5) are not stored as they can be generated more efficiently. */
+#define V_LOG1PF_CONSTANTS_TABLE \
+ { \
+ .poly \
+ = { V4 (0x1.5555aap-2f), V4 (-0x1.000038p-2f), V4 (0x1.99675cp-3f), \
+ V4 (-0x1.54ef78p-3f), V4 (0x1.28a1f4p-3f), V4 (-0x1.0da91p-3f), \
+ V4 (0x1.abcb6p-4f), V4 (-0x1.6f0d5ep-5f) }, \
+ .ln2 = V4 (0x1.62e43p-1f), .four = V4 (0x40800000), \
+ .three_quarters = V4 (0x3f400000) \
+ }
+
+static inline float32x4_t
+eval_poly (float32x4_t m, const float32x4_t *c)
+{
+ /* Approximate log(1+m) on [-0.25, 0.5] using pairwise Horner (main routine
+ uses split Estrin, but this way reduces register pressure in the calling
+ routine). */
+ float32x4_t q = vfmaq_f32 (v_f32 (-0.5), m, c[0]);
+ float32x4_t m2 = vmulq_f32 (m, m);
+ q = vfmaq_f32 (m, m2, q);
+ float32x4_t p = v_pw_horner_6_f32 (m, m2, c + 1);
+ p = vmulq_f32 (m2, p);
+ return vfmaq_f32 (q, m2, p);
+}
+
+static inline float32x4_t
+log1pf_inline (float32x4_t x, const struct v_log1pf_data d)
+{
+ /* Helper for calculating log(x + 1). Copied from log1pf_2u1.c, with no
+ special-case handling. See that file for details of the algorithm. */
+ float32x4_t m = vaddq_f32 (x, v_f32 (1.0f));
+ int32x4_t k
+ = vandq_s32 (vsubq_s32 (vreinterpretq_s32_f32 (m), d.three_quarters),
+ v_s32 (0xff800000));
+ uint32x4_t ku = vreinterpretq_u32_s32 (k);
+ float32x4_t s = vreinterpretq_f32_u32 (vsubq_u32 (d.four, ku));
+ float32x4_t m_scale
+ = vreinterpretq_f32_u32 (vsubq_u32 (vreinterpretq_u32_f32 (x), ku));
+ m_scale = vaddq_f32 (m_scale, vfmaq_f32 (v_f32 (-1.0f), v_f32 (0.25f), s));
+ float32x4_t p = eval_poly (m_scale, d.poly);
+ float32x4_t scale_back = vmulq_f32 (vcvtq_f32_s32 (k), v_f32 (0x1.0p-23f));
+ return vfmaq_f32 (p, scale_back, d.ln2);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/v_math.h b/sysdeps/aarch64/fpu/v_math.h
index d4d78bc402..12824fce8c 100644
--- a/sysdeps/aarch64/fpu/v_math.h
+++ b/sysdeps/aarch64/fpu/v_math.h
@@ -108,6 +108,11 @@ v_call2_f32 (float (*f) (float, float), float32x4_t x1, float32x4_t x2,
p[2] ? f (x1[2], x2[2]) : y[2],
p[3] ? f (x1[3], x2[3]) : y[3] };
}
+static inline float32x4_t
+v_zerofy_f32 (float32x4_t x, uint32x4_t mask)
+{
+ return vreinterpretq_f32_u32 (vbicq_u32 (vreinterpretq_u32_f32 (x), mask));
+}
static inline float64x2_t
v_f64 (double x)
@@ -167,5 +172,10 @@ v_call2_f64 (double (*f) (double, double), float64x2_t x1, float64x2_t x2,
return (float64x2_t){ p[0] ? f (x1[0], x2[0]) : y[0],
p[1] ? f (x1[1], x2[1]) : y[1] };
}
+static inline float64x2_t
+v_zerofy_f64 (float64x2_t x, uint64x2_t mask)
+{
+ return vreinterpretq_f64_u64 (vbicq_u64 (vreinterpretq_u64_f64 (x), mask));
+}
#endif
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index 97f45236dd..3afdd35043 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -34,11 +34,19 @@ double: 2
float: 2
ldouble: 4
+Function: "acosh_advsimd":
+double: 2
+float: 2
+
Function: "acosh_downward":
double: 2
float: 2
ldouble: 3
+Function: "acosh_sve":
+double: 2
+float: 2
+
Function: "acosh_towardzero":
double: 2
float: 2
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index f66da42c36..f5aaa519f2 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -73,12 +73,17 @@ GLIBC_2.39 _ZGVsMxv_tan F
GLIBC_2.39 _ZGVsMxv_tanf F
GLIBC_2.39 _ZGVsMxvv_atan2 F
GLIBC_2.39 _ZGVsMxvv_atan2f F
+GLIBC_2.40 _ZGVnN2v_acosh F
+GLIBC_2.40 _ZGVnN2v_acoshf F
GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
+GLIBC_2.40 _ZGVnN4v_acoshf F
GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
+GLIBC_2.40 _ZGVsMxv_acosh F
+GLIBC_2.40 _ZGVsMxv_acoshf F
GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/8] aarch64/fpu: Add vector variants of asinh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
2024-02-20 16:59 ` [PATCH 2/8] aarch64/fpu: Add vector variants of cosh Joe Ramsay
2024-02-20 16:59 ` [PATCH 3/8] aarch64/fpu: Add vector variants of acosh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:44 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 5/8] aarch64/fpu: Add vector variants of atanh Joe Ramsay
` (4 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 1 +
sysdeps/aarch64/fpu/Versions | 5 +
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/asinh_advsimd.c | 171 ++++++++++++++++++
sysdeps/aarch64/fpu/asinh_sve.c | 150 +++++++++++++++
sysdeps/aarch64/fpu/asinhf_advsimd.c | 80 ++++++++
sysdeps/aarch64/fpu/asinhf_sve.c | 56 ++++++
sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/libm-test-ulps | 8 +
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
14 files changed, 489 insertions(+)
create mode 100644 sysdeps/aarch64/fpu/asinh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/asinh_sve.c
create mode 100644 sysdeps/aarch64/fpu/asinhf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/asinhf_sve.c
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index 2e5bbb5a07..d474f2969d 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -1,6 +1,7 @@
libmvec-supported-funcs = acos \
acosh \
asin \
+ asinh \
atan \
atan2 \
cos \
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 60e1cdeace..08ea15efae 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -84,6 +84,11 @@ libmvec {
_ZGVnN4v_acoshf;
_ZGVsMxv_acosh;
_ZGVsMxv_acoshf;
+ _ZGVnN2v_asinh;
+ _ZGVnN2v_asinhf;
+ _ZGVnN4v_asinhf;
+ _ZGVsMxv_asinh;
+ _ZGVsMxv_asinhf;
_ZGVnN2v_cosh;
_ZGVnN2v_coshf;
_ZGVnN4v_coshf;
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index 22fec4de77..1e80721c9f 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -20,6 +20,7 @@
libmvec_hidden_proto (V_NAME_F1(acos));
libmvec_hidden_proto (V_NAME_F1(acosh));
libmvec_hidden_proto (V_NAME_F1(asin));
+libmvec_hidden_proto (V_NAME_F1(asinh));
libmvec_hidden_proto (V_NAME_F1(atan));
libmvec_hidden_proto (V_NAME_F1(cos));
libmvec_hidden_proto (V_NAME_F1(cosh));
diff --git a/sysdeps/aarch64/fpu/asinh_advsimd.c b/sysdeps/aarch64/fpu/asinh_advsimd.c
new file mode 100644
index 0000000000..544a52f651
--- /dev/null
+++ b/sysdeps/aarch64/fpu/asinh_advsimd.c
@@ -0,0 +1,171 @@
+/* Double-precision vector (Advanced SIMD) asinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "poly_advsimd_f64.h"
+
+#define A(i) v_f64 (__v_log_data.poly[i])
+#define N (1 << V_LOG_TABLE_BITS)
+
+const static struct data
+{
+ float64x2_t poly[18];
+ uint64x2_t off, huge_bound, abs_mask;
+ float64x2_t ln2, tiny_bound;
+} data = {
+ .off = V2 (0x3fe6900900000000),
+ .ln2 = V2 (0x1.62e42fefa39efp-1),
+ .huge_bound = V2 (0x5fe0000000000000),
+ .tiny_bound = V2 (0x1p-26),
+ .abs_mask = V2 (0x7fffffffffffffff),
+ /* Even terms of polynomial s.t. asinh(x) is approximated by
+ asinh(x) ~= x + x^3 * (C0 + C1 * x + C2 * x^2 + C3 * x^3 + ...).
+ Generated using Remez, f = (asinh(sqrt(x)) - sqrt(x))/x^(3/2). */
+ .poly = { V2 (-0x1.55555555554a7p-3), V2 (0x1.3333333326c7p-4),
+ V2 (-0x1.6db6db68332e6p-5), V2 (0x1.f1c71b26fb40dp-6),
+ V2 (-0x1.6e8b8b654a621p-6), V2 (0x1.1c4daa9e67871p-6),
+ V2 (-0x1.c9871d10885afp-7), V2 (0x1.7a16e8d9d2ecfp-7),
+ V2 (-0x1.3ddca533e9f54p-7), V2 (0x1.0becef748dafcp-7),
+ V2 (-0x1.b90c7099dd397p-8), V2 (0x1.541f2bb1ffe51p-8),
+ V2 (-0x1.d217026a669ecp-9), V2 (0x1.0b5c7977aaf7p-9),
+ V2 (-0x1.e0f37daef9127p-11), V2 (0x1.388b5fe542a6p-12),
+ V2 (-0x1.021a48685e287p-14), V2 (0x1.93d4ba83d34dap-18) },
+};
+
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
+{
+ return v_call_f64 (asinh, x, y, special);
+}
+
+struct entry
+{
+ float64x2_t invc;
+ float64x2_t logc;
+};
+
+static inline struct entry
+lookup (uint64x2_t i)
+{
+ float64x2_t e0 = vld1q_f64 (
+ &__v_log_data.table[(i[0] >> (52 - V_LOG_TABLE_BITS)) & (N - 1)].invc);
+ float64x2_t e1 = vld1q_f64 (
+ &__v_log_data.table[(i[1] >> (52 - V_LOG_TABLE_BITS)) & (N - 1)].invc);
+ return (struct entry){ vuzp1q_f64 (e0, e1), vuzp2q_f64 (e0, e1) };
+}
+
+static inline float64x2_t
+log_inline (float64x2_t x, const struct data *d)
+{
+ /* Double-precision vector log, copied from ordinary vector log with some
+ cosmetic modification and special-cases removed. */
+ uint64x2_t ix = vreinterpretq_u64_f64 (x);
+ uint64x2_t tmp = vsubq_u64 (ix, d->off);
+ int64x2_t k = vshrq_n_s64 (vreinterpretq_s64_u64 (tmp), 52);
+ uint64x2_t iz
+ = vsubq_u64 (ix, vandq_u64 (tmp, vdupq_n_u64 (0xfffULL << 52)));
+ float64x2_t z = vreinterpretq_f64_u64 (iz);
+ struct entry e = lookup (tmp);
+ float64x2_t r = vfmaq_f64 (v_f64 (-1.0), z, e.invc);
+ float64x2_t kd = vcvtq_f64_s64 (k);
+ float64x2_t hi = vfmaq_f64 (vaddq_f64 (e.logc, r), kd, d->ln2);
+ float64x2_t r2 = vmulq_f64 (r, r);
+ float64x2_t y = vfmaq_f64 (A (2), A (3), r);
+ float64x2_t p = vfmaq_f64 (A (0), A (1), r);
+ y = vfmaq_f64 (y, A (4), r2);
+ y = vfmaq_f64 (p, y, r2);
+ y = vfmaq_f64 (hi, y, r2);
+ return y;
+}
+
+/* Double-precision implementation of vector asinh(x).
+ asinh is very sensitive around 1, so it is impractical to devise a single
+ low-cost algorithm which is sufficiently accurate on a wide range of input.
+ Instead we use two different algorithms:
+ asinh(x) = sign(x) * log(|x| + sqrt(x^2 + 1) if |x| >= 1
+ = sign(x) * (|x| + |x|^3 * P(x^2)) otherwise
+ where log(x) is an optimized log approximation, and P(x) is a polynomial
+ shared with the scalar routine. The greatest observed error 3.29 ULP, in
+ |x| >= 1:
+ __v_asinh(0x1.2cd9d717e2c9bp+0) got 0x1.ffffcfd0e234fp-1
+ want 0x1.ffffcfd0e2352p-1. */
+VPCS_ATTR float64x2_t V_NAME_D1 (asinh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float64x2_t ax = vabsq_f64 (x);
+ uint64x2_t iax = vreinterpretq_u64_f64 (ax);
+
+ uint64x2_t gt1 = vcgeq_f64 (ax, v_f64 (1));
+ uint64x2_t special = vcgeq_u64 (iax, d->huge_bound);
+
+#if WANT_SIMD_EXCEPT
+ uint64x2_t tiny = vcltq_f64 (ax, d->tiny_bound);
+ special = vorrq_u64 (special, tiny);
+#endif
+
+ /* Option 1: |x| >= 1.
+ Compute asinh(x) according by asinh(x) = log(x + sqrt(x^2 + 1)).
+ If WANT_SIMD_EXCEPT is enabled, sidestep special values, which will
+ overflow, by setting special lanes to 1. These will be fixed later. */
+ float64x2_t option_1 = v_f64 (0);
+ if (__glibc_likely (v_any_u64 (gt1)))
+ {
+#if WANT_SIMD_EXCEPT
+ float64x2_t xm = v_zerofy_f64 (ax, special);
+#else
+ float64x2_t xm = ax;
+#endif
+ option_1 = log_inline (
+ vaddq_f64 (xm, vsqrtq_f64 (vfmaq_f64 (v_f64 (1), xm, xm))), d);
+ }
+
+ /* Option 2: |x| < 1.
+ Compute asinh(x) using a polynomial.
+ If WANT_SIMD_EXCEPT is enabled, sidestep special lanes, which will
+ overflow, and tiny lanes, which will underflow, by setting them to 0. They
+ will be fixed later, either by selecting x or falling back to the scalar
+ special-case. The largest observed error in this region is 1.47 ULPs:
+ __v_asinh(0x1.fdfcd00cc1e6ap-1) got 0x1.c1d6bf874019bp-1
+ want 0x1.c1d6bf874019cp-1. */
+ float64x2_t option_2 = v_f64 (0);
+ if (__glibc_likely (v_any_u64 (vceqzq_u64 (gt1))))
+ {
+#if WANT_SIMD_EXCEPT
+ ax = v_zerofy_f64 (ax, vorrq_u64 (tiny, gt1));
+#endif
+ float64x2_t x2 = vmulq_f64 (ax, ax), x3 = vmulq_f64 (ax, x2),
+ z2 = vmulq_f64 (x2, x2), z4 = vmulq_f64 (z2, z2),
+ z8 = vmulq_f64 (z4, z4), z16 = vmulq_f64 (z8, z8);
+ float64x2_t p = v_estrin_17_f64 (x2, z2, z4, z8, z16, d->poly);
+ option_2 = vfmaq_f64 (ax, p, x3);
+#if WANT_SIMD_EXCEPT
+ option_2 = vbslq_f64 (tiny, x, option_2);
+#endif
+ }
+
+ /* Choose the right option for each lane. */
+ float64x2_t y = vbslq_f64 (gt1, option_1, option_2);
+ /* Copy sign. */
+ y = vbslq_f64 (d->abs_mask, y, x);
+
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (x, y, special);
+ return y;
+}
diff --git a/sysdeps/aarch64/fpu/asinh_sve.c b/sysdeps/aarch64/fpu/asinh_sve.c
new file mode 100644
index 0000000000..28dc5c4587
--- /dev/null
+++ b/sysdeps/aarch64/fpu/asinh_sve.c
@@ -0,0 +1,150 @@
+/* Double-precision vector (SVE) asinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "poly_sve_f64.h"
+
+#define SignMask (0x8000000000000000)
+#define One (0x3ff0000000000000)
+#define Thres (0x5fe0000000000000) /* asuint64 (0x1p511). */
+
+static const struct data
+{
+ double poly[18];
+ double ln2, p3, p1, p4, p0, p2;
+ uint64_t n;
+ uint64_t off;
+
+} data = {
+ /* Polynomial generated using Remez on [2^-26, 1]. */
+ .poly
+ = { -0x1.55555555554a7p-3, 0x1.3333333326c7p-4, -0x1.6db6db68332e6p-5,
+ 0x1.f1c71b26fb40dp-6, -0x1.6e8b8b654a621p-6, 0x1.1c4daa9e67871p-6,
+ -0x1.c9871d10885afp-7, 0x1.7a16e8d9d2ecfp-7, -0x1.3ddca533e9f54p-7,
+ 0x1.0becef748dafcp-7, -0x1.b90c7099dd397p-8, 0x1.541f2bb1ffe51p-8,
+ -0x1.d217026a669ecp-9, 0x1.0b5c7977aaf7p-9, -0x1.e0f37daef9127p-11,
+ 0x1.388b5fe542a6p-12, -0x1.021a48685e287p-14, 0x1.93d4ba83d34dap-18 },
+ .ln2 = 0x1.62e42fefa39efp-1,
+ .p0 = -0x1.ffffffffffff7p-2,
+ .p1 = 0x1.55555555170d4p-2,
+ .p2 = -0x1.0000000399c27p-2,
+ .p3 = 0x1.999b2e90e94cap-3,
+ .p4 = -0x1.554e550bd501ep-3,
+ .n = 1 << V_LOG_TABLE_BITS,
+ .off = 0x3fe6900900000000
+};
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
+{
+ return sv_call_f64 (asinh, x, y, special);
+}
+
+static inline svfloat64_t
+__sv_log_inline (svfloat64_t x, const struct data *d, const svbool_t pg)
+{
+ /* Double-precision SVE log, copied from SVE log implementation with some
+ cosmetic modification and special-cases removed. See that file for details
+ of the algorithm used. */
+
+ svuint64_t ix = svreinterpret_u64 (x);
+ svuint64_t tmp = svsub_x (pg, ix, d->off);
+ svuint64_t i = svand_x (pg, svlsr_x (pg, tmp, (51 - V_LOG_TABLE_BITS)),
+ (d->n - 1) << 1);
+ svint64_t k = svasr_x (pg, svreinterpret_s64 (tmp), 52);
+ svuint64_t iz = svsub_x (pg, ix, svand_x (pg, tmp, 0xfffULL << 52));
+ svfloat64_t z = svreinterpret_f64 (iz);
+
+ svfloat64_t invc = svld1_gather_index (pg, &__v_log_data.table[0].invc, i);
+ svfloat64_t logc = svld1_gather_index (pg, &__v_log_data.table[0].logc, i);
+
+ svfloat64_t ln2_p3 = svld1rq (svptrue_b64 (), &d->ln2);
+ svfloat64_t p1_p4 = svld1rq (svptrue_b64 (), &d->p1);
+
+ svfloat64_t r = svmla_x (pg, sv_f64 (-1.0), invc, z);
+ svfloat64_t kd = svcvt_f64_x (pg, k);
+
+ svfloat64_t hi = svmla_lane (svadd_x (pg, logc, r), kd, ln2_p3, 0);
+ svfloat64_t r2 = svmul_x (pg, r, r);
+
+ svfloat64_t y = svmla_lane (sv_f64 (d->p2), r, ln2_p3, 1);
+
+ svfloat64_t p = svmla_lane (sv_f64 (d->p0), r, p1_p4, 0);
+ y = svmla_lane (y, r2, p1_p4, 1);
+ y = svmla_x (pg, p, r2, y);
+ y = svmla_x (pg, hi, r2, y);
+ return y;
+}
+
+/* Double-precision implementation of SVE asinh(x).
+ asinh is very sensitive around 1, so it is impractical to devise a single
+ low-cost algorithm which is sufficiently accurate on a wide range of input.
+ Instead we use two different algorithms:
+ asinh(x) = sign(x) * log(|x| + sqrt(x^2 + 1) if |x| >= 1
+ = sign(x) * (|x| + |x|^3 * P(x^2)) otherwise
+ where log(x) is an optimized log approximation, and P(x) is a polynomial
+ shared with the scalar routine. The greatest observed error 2.51 ULP, in
+ |x| >= 1:
+ _ZGVsMxv_asinh(0x1.170469d024505p+0) got 0x1.e3181c43b0f36p-1
+ want 0x1.e3181c43b0f39p-1. */
+svfloat64_t SV_NAME_D1 (asinh) (svfloat64_t x, const svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svuint64_t ix = svreinterpret_u64 (x);
+ svuint64_t iax = svbic_x (pg, ix, SignMask);
+ svuint64_t sign = svand_x (pg, ix, SignMask);
+ svfloat64_t ax = svreinterpret_f64 (iax);
+
+ svbool_t ge1 = svcmpge (pg, iax, One);
+ svbool_t special = svcmpge (pg, iax, Thres);
+
+ /* Option 1: |x| >= 1.
+ Compute asinh(x) according by asinh(x) = log(x + sqrt(x^2 + 1)). */
+ svfloat64_t option_1 = sv_f64 (0);
+ if (__glibc_likely (svptest_any (pg, ge1)))
+ {
+ svfloat64_t x2 = svmul_x (pg, ax, ax);
+ option_1 = __sv_log_inline (
+ svadd_x (pg, ax, svsqrt_x (pg, svadd_x (pg, x2, 1))), d, pg);
+ }
+
+ /* Option 2: |x| < 1.
+ Compute asinh(x) using a polynomial.
+ The largest observed error in this region is 1.51 ULPs:
+ _ZGVsMxv_asinh(0x1.fe12bf8c616a2p-1) got 0x1.c1e649ee2681bp-1
+ want 0x1.c1e649ee2681dp-1. */
+ svfloat64_t option_2 = sv_f64 (0);
+ if (__glibc_likely (svptest_any (pg, svnot_z (pg, ge1))))
+ {
+ svfloat64_t x2 = svmul_x (pg, ax, ax);
+ svfloat64_t x4 = svmul_x (pg, x2, x2);
+ svfloat64_t p = sv_pw_horner_17_f64_x (pg, x2, x4, d->poly);
+ option_2 = svmla_x (pg, ax, p, svmul_x (pg, x2, ax));
+ }
+
+ /* Choose the right option for each lane. */
+ svfloat64_t y = svsel (ge1, option_1, option_2);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (
+ x, svreinterpret_f64 (sveor_x (pg, svreinterpret_u64 (y), sign)),
+ special);
+ return svreinterpret_f64 (sveor_x (pg, svreinterpret_u64 (y), sign));
+}
diff --git a/sysdeps/aarch64/fpu/asinhf_advsimd.c b/sysdeps/aarch64/fpu/asinhf_advsimd.c
new file mode 100644
index 0000000000..09fd8a6143
--- /dev/null
+++ b/sysdeps/aarch64/fpu/asinhf_advsimd.c
@@ -0,0 +1,80 @@
+/* Single-precision vector (Advanced SIMD) asinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "v_log1pf_inline.h"
+
+#define SignMask v_u32 (0x80000000)
+
+const static struct data
+{
+ struct v_log1pf_data log1pf_consts;
+ uint32x4_t big_bound;
+#if WANT_SIMD_EXCEPT
+ uint32x4_t tiny_bound;
+#endif
+} data = {
+ .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
+ .big_bound = V4 (0x5f800000), /* asuint(0x1p64). */
+#if WANT_SIMD_EXCEPT
+ .tiny_bound = V4 (0x30800000) /* asuint(0x1p-30). */
+#endif
+};
+
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
+{
+ return v_call_f32 (asinhf, x, y, special);
+}
+
+/* Single-precision implementation of vector asinh(x), using vector log1p.
+ Worst-case error is 2.66 ULP, at roughly +/-0.25:
+ __v_asinhf(0x1.01b04p-2) got 0x1.fe163ep-3 want 0x1.fe1638p-3. */
+VPCS_ATTR float32x4_t NOINLINE V_NAME_F1 (asinh) (float32x4_t x)
+{
+ const struct data *dat = ptr_barrier (&data);
+ uint32x4_t iax = vbicq_u32 (vreinterpretq_u32_f32 (x), SignMask);
+ float32x4_t ax = vreinterpretq_f32_u32 (iax);
+ uint32x4_t special = vcgeq_u32 (iax, dat->big_bound);
+ float32x4_t special_arg = x;
+
+#if WANT_SIMD_EXCEPT
+ /* Sidestep tiny and large values to avoid inadvertently triggering
+ under/overflow. */
+ special = vorrq_u32 (special, vcltq_u32 (iax, dat->tiny_bound));
+ if (__glibc_unlikely (v_any_u32 (special)))
+ {
+ ax = v_zerofy_f32 (ax, special);
+ x = v_zerofy_f32 (x, special);
+ }
+#endif
+
+ /* asinh(x) = log(x + sqrt(x * x + 1)).
+ For positive x, asinh(x) = log1p(x + x * x / (1 + sqrt(x * x + 1))). */
+ float32x4_t d
+ = vaddq_f32 (v_f32 (1), vsqrtq_f32 (vfmaq_f32 (v_f32 (1), x, x)));
+ float32x4_t y = log1pf_inline (
+ vaddq_f32 (ax, vdivq_f32 (vmulq_f32 (ax, ax), d)), dat->log1pf_consts);
+
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return special_case (special_arg, vbslq_f32 (SignMask, x, y), special);
+ return vbslq_f32 (SignMask, x, y);
+}
+libmvec_hidden_def (V_NAME_F1 (asinh))
+HALF_WIDTH_ALIAS_F1 (asinh)
diff --git a/sysdeps/aarch64/fpu/asinhf_sve.c b/sysdeps/aarch64/fpu/asinhf_sve.c
new file mode 100644
index 0000000000..d85c3a685c
--- /dev/null
+++ b/sysdeps/aarch64/fpu/asinhf_sve.c
@@ -0,0 +1,56 @@
+/* Single-precision vector (SVE) asinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "sv_log1pf_inline.h"
+
+#define BigBound (0x5f800000) /* asuint(0x1p64). */
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t special)
+{
+ return sv_call_f32 (asinhf, x, y, special);
+}
+
+/* Single-precision SVE asinh(x) routine. Implements the same algorithm as
+ vector asinhf and log1p.
+
+ Maximum error is 2.48 ULPs:
+ SV_NAME_F1 (asinh) (0x1.008864p-3) got 0x1.ffbbbcp-4
+ want 0x1.ffbbb8p-4. */
+svfloat32_t SV_NAME_F1 (asinh) (svfloat32_t x, const svbool_t pg)
+{
+ svfloat32_t ax = svabs_x (pg, x);
+ svuint32_t iax = svreinterpret_u32 (ax);
+ svuint32_t sign = sveor_x (pg, svreinterpret_u32 (x), iax);
+ svbool_t special = svcmpge (pg, iax, BigBound);
+
+ /* asinh(x) = log(x + sqrt(x * x + 1)).
+ For positive x, asinh(x) = log1p(x + x * x / (1 + sqrt(x * x + 1))). */
+ svfloat32_t ax2 = svmul_x (pg, ax, ax);
+ svfloat32_t d = svadd_x (pg, svsqrt_x (pg, svadd_x (pg, ax2, 1.0f)), 1.0f);
+ svfloat32_t y
+ = sv_log1pf_inline (svadd_x (pg, ax, svdiv_x (pg, ax2, d)), pg);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (
+ x, svreinterpret_f32 (svorr_x (pg, sign, svreinterpret_u32 (y))),
+ special);
+ return svreinterpret_f32 (svorr_x (pg, sign, svreinterpret_u32 (y)));
+}
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 841330956c..eb2af35b27 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -41,6 +41,10 @@
# define __DECL_SIMD_asin __DECL_SIMD_aarch64
# undef __DECL_SIMD_asinf
# define __DECL_SIMD_asinf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_asinh
+# define __DECL_SIMD_asinh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_asinhf
+# define __DECL_SIMD_asinhf __DECL_SIMD_aarch64
# undef __DECL_SIMD_atan
# define __DECL_SIMD_atan __DECL_SIMD_aarch64
# undef __DECL_SIMD_atanf
@@ -131,6 +135,7 @@ __vpcs __f32x4_t _ZGVnN4vv_atan2f (__f32x4_t, __f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_acosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_acoshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_asinhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t);
@@ -150,6 +155,7 @@ __vpcs __f64x2_t _ZGVnN2vv_atan2 (__f64x2_t, __f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_acosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_asinh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t);
@@ -174,6 +180,7 @@ __sv_f32_t _ZGVsMxvv_atan2f (__sv_f32_t, __sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_acosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_acoshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_asinhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t);
@@ -193,6 +200,7 @@ __sv_f64_t _ZGVsMxvv_atan2 (__sv_f64_t, __sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_acosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_asinh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index f4ce1d7009..3d7177c32d 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -26,6 +26,7 @@
VPCS_VECTOR_WRAPPER (acos_advsimd, _ZGVnN2v_acos)
VPCS_VECTOR_WRAPPER (acosh_advsimd, _ZGVnN2v_acosh)
VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
+VPCS_VECTOR_WRAPPER (asinh_advsimd, _ZGVnN2v_asinh)
VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 0e973cc9d7..b88a2afe5c 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -45,6 +45,7 @@
SVE_VECTOR_WRAPPER (acos_sve, _ZGVsMxv_acos)
SVE_VECTOR_WRAPPER (acosh_sve, _ZGVsMxv_acosh)
SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin)
+SVE_VECTOR_WRAPPER (asinh_sve, _ZGVsMxv_asinh)
SVE_VECTOR_WRAPPER (atan_sve, _ZGVsMxv_atan)
SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 0ce026b5ea..533655402d 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -26,6 +26,7 @@
VPCS_VECTOR_WRAPPER (acosf_advsimd, _ZGVnN4v_acosf)
VPCS_VECTOR_WRAPPER (acoshf_advsimd, _ZGVnN4v_acoshf)
VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
+VPCS_VECTOR_WRAPPER (asinhf_advsimd, _ZGVnN4v_asinhf)
VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index 398b7373e8..f7b673e335 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -45,6 +45,7 @@
SVE_VECTOR_WRAPPER (acosf_sve, _ZGVsMxv_acosf)
SVE_VECTOR_WRAPPER (acoshf_sve, _ZGVsMxv_acoshf)
SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf)
+SVE_VECTOR_WRAPPER (asinhf_sve, _ZGVsMxv_asinhf)
SVE_VECTOR_WRAPPER (atanf_sve, _ZGVsMxv_atanf)
SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf)
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index 3afdd35043..dc8cb08b3a 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -90,11 +90,19 @@ double: 2
float: 2
ldouble: 4
+Function: "asinh_advsimd":
+double: 1
+float: 2
+
Function: "asinh_downward":
double: 3
float: 3
ldouble: 4
+Function: "asinh_sve":
+double: 1
+float: 2
+
Function: "asinh_towardzero":
double: 2
float: 2
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index f5aaa519f2..f288afdfdd 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -75,15 +75,20 @@ GLIBC_2.39 _ZGVsMxvv_atan2 F
GLIBC_2.39 _ZGVsMxvv_atan2f F
GLIBC_2.40 _ZGVnN2v_acosh F
GLIBC_2.40 _ZGVnN2v_acoshf F
+GLIBC_2.40 _ZGVnN2v_asinh F
+GLIBC_2.40 _ZGVnN2v_asinhf F
GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
GLIBC_2.40 _ZGVnN4v_acoshf F
+GLIBC_2.40 _ZGVnN4v_asinhf F
GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
GLIBC_2.40 _ZGVsMxv_acosh F
GLIBC_2.40 _ZGVsMxv_acoshf F
+GLIBC_2.40 _ZGVsMxv_asinh F
+GLIBC_2.40 _ZGVsMxv_asinhf F
GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/8] aarch64/fpu: Add vector variants of atanh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
` (2 preceding siblings ...)
2024-02-20 16:59 ` [PATCH 4/8] aarch64/fpu: Add vector variants of asinh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:45 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 6/8] aarch64/fpu: Add vector variants of sinh Joe Ramsay
` (3 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 1 +
sysdeps/aarch64/fpu/Versions | 5 ++
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/atanh_advsimd.c | 64 +++++++++++++++
sysdeps/aarch64/fpu/atanh_sve.c | 59 ++++++++++++++
sysdeps/aarch64/fpu/atanhf_advsimd.c | 79 +++++++++++++++++++
sysdeps/aarch64/fpu/atanhf_sve.c | 54 +++++++++++++
sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/libm-test-ulps | 8 ++
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 ++
14 files changed, 288 insertions(+)
create mode 100644 sysdeps/aarch64/fpu/atanh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/atanh_sve.c
create mode 100644 sysdeps/aarch64/fpu/atanhf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/atanhf_sve.c
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index d474f2969d..4c878e5906 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -3,6 +3,7 @@ libmvec-supported-funcs = acos \
asin \
asinh \
atan \
+ atanh \
atan2 \
cos \
cosh \
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 08ea15efae..86c08c1fa3 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -99,5 +99,10 @@ libmvec {
_ZGVnN4v_erff;
_ZGVsMxv_erf;
_ZGVsMxv_erff;
+ _ZGVnN2v_atanh;
+ _ZGVnN2v_atanhf;
+ _ZGVnN4v_atanhf;
+ _ZGVsMxv_atanh;
+ _ZGVsMxv_atanhf;
}
}
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index 1e80721c9f..afbb01e191 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -22,6 +22,7 @@ libmvec_hidden_proto (V_NAME_F1(acosh));
libmvec_hidden_proto (V_NAME_F1(asin));
libmvec_hidden_proto (V_NAME_F1(asinh));
libmvec_hidden_proto (V_NAME_F1(atan));
+libmvec_hidden_proto (V_NAME_F1(atanh));
libmvec_hidden_proto (V_NAME_F1(cos));
libmvec_hidden_proto (V_NAME_F1(cosh));
libmvec_hidden_proto (V_NAME_F1(erf));
diff --git a/sysdeps/aarch64/fpu/atanh_advsimd.c b/sysdeps/aarch64/fpu/atanh_advsimd.c
new file mode 100644
index 0000000000..3c3d0bd6ad
--- /dev/null
+++ b/sysdeps/aarch64/fpu/atanh_advsimd.c
@@ -0,0 +1,64 @@
+/* Double-precision vector (Advanced SIMD) atanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WANT_V_LOG1P_K0_SHORTCUT 0
+#include "v_log1p_inline.h"
+
+const static struct data
+{
+ struct v_log1p_data log1p_consts;
+ uint64x2_t one, half;
+} data = { .log1p_consts = V_LOG1P_CONSTANTS_TABLE,
+ .one = V2 (0x3ff0000000000000),
+ .half = V2 (0x3fe0000000000000) };
+
+static float64x2_t VPCS_ATTR NOINLINE
+special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
+{
+ return v_call_f64 (atanh, x, y, special);
+}
+
+/* Approximation for vector double-precision atanh(x) using modified log1p.
+ The greatest observed error is 3.31 ULP:
+ _ZGVnN2v_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6
+ want 0x1.ffd8ff31b501cp-6. */
+VPCS_ATTR
+float64x2_t V_NAME_D1 (atanh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float64x2_t ax = vabsq_f64 (x);
+ uint64x2_t ia = vreinterpretq_u64_f64 (ax);
+ uint64x2_t sign = veorq_u64 (vreinterpretq_u64_f64 (x), ia);
+ uint64x2_t special = vcgeq_u64 (ia, d->one);
+ float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->half));
+
+#if WANT_SIMD_EXCEPT
+ ax = v_zerofy_f64 (ax, special);
+#endif
+
+ float64x2_t y;
+ y = vaddq_f64 (ax, ax);
+ y = vdivq_f64 (y, vsubq_f64 (v_f64 (1), ax));
+ y = log1p_inline (y, &d->log1p_consts);
+
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (x, vmulq_f64 (y, halfsign), special);
+ return vmulq_f64 (y, halfsign);
+}
diff --git a/sysdeps/aarch64/fpu/atanh_sve.c b/sysdeps/aarch64/fpu/atanh_sve.c
new file mode 100644
index 0000000000..7a52728d70
--- /dev/null
+++ b/sysdeps/aarch64/fpu/atanh_sve.c
@@ -0,0 +1,59 @@
+/* Double-precision vector (SVE) atanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#define WANT_SV_LOG1P_K0_SHORTCUT 0
+#include "sv_log1p_inline.h"
+
+#define One (0x3ff0000000000000)
+#define Half (0x3fe0000000000000)
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
+{
+ return sv_call_f64 (atanh, x, y, special);
+}
+
+/* SVE approximation for double-precision atanh, based on log1p.
+ The greatest observed error is 2.81 ULP:
+ _ZGVsMxv_atanh(0x1.ffae6288b601p-6) got 0x1.ffd8ff31b5019p-6
+ want 0x1.ffd8ff31b501cp-6. */
+svfloat64_t SV_NAME_D1 (atanh) (svfloat64_t x, const svbool_t pg)
+{
+
+ svfloat64_t ax = svabs_x (pg, x);
+ svuint64_t iax = svreinterpret_u64 (ax);
+ svuint64_t sign = sveor_x (pg, svreinterpret_u64 (x), iax);
+ svfloat64_t halfsign = svreinterpret_f64 (svorr_x (pg, sign, Half));
+
+ /* It is special if iax >= 1. */
+// svbool_t special = svcmpge (pg, iax, One);
+ svbool_t special = svacge (pg, x, 1.0);
+
+ /* Computation is performed based on the following sequence of equality:
+ (1+x)/(1-x) = 1 + 2x/(1-x). */
+ svfloat64_t y;
+ y = svadd_x (pg, ax, ax);
+ y = svdiv_x (pg, y, svsub_x (pg, sv_f64 (1), ax));
+ /* ln((1+x)/(1-x)) = ln(1+2x/(1-x)) = ln(1 + y). */
+ y = sv_log1p_inline (y, pg);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svmul_x (pg, halfsign, y), special);
+ return svmul_x (pg, halfsign, y);
+}
diff --git a/sysdeps/aarch64/fpu/atanhf_advsimd.c b/sysdeps/aarch64/fpu/atanhf_advsimd.c
new file mode 100644
index 0000000000..ae488f7b54
--- /dev/null
+++ b/sysdeps/aarch64/fpu/atanhf_advsimd.c
@@ -0,0 +1,79 @@
+/* Single-precision vector (Advanced SIMD) atanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "v_log1pf_inline.h"
+
+const static struct data
+{
+ struct v_log1pf_data log1pf_consts;
+ uint32x4_t one;
+#if WANT_SIMD_EXCEPT
+ uint32x4_t tiny_bound;
+#endif
+} data = {
+ .log1pf_consts = V_LOG1PF_CONSTANTS_TABLE,
+ .one = V4 (0x3f800000),
+#if WANT_SIMD_EXCEPT
+ /* 0x1p-12, below which atanhf(x) rounds to x. */
+ .tiny_bound = V4 (0x39800000),
+#endif
+};
+
+#define AbsMask v_u32 (0x7fffffff)
+#define Half v_u32 (0x3f000000)
+
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
+{
+ return v_call_f32 (atanhf, x, y, special);
+}
+
+/* Approximation for vector single-precision atanh(x) using modified log1p.
+ The maximum error is 3.08 ULP:
+ __v_atanhf(0x1.ff215p-5) got 0x1.ffcb7cp-5
+ want 0x1.ffcb82p-5. */
+VPCS_ATTR float32x4_t NOINLINE V_NAME_F1 (atanh) (float32x4_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float32x4_t halfsign = vbslq_f32 (AbsMask, v_f32 (0.5), x);
+ float32x4_t ax = vabsq_f32 (x);
+ uint32x4_t iax = vreinterpretq_u32_f32 (ax);
+
+#if WANT_SIMD_EXCEPT
+ uint32x4_t special
+ = vorrq_u32 (vcgeq_u32 (iax, d->one), vcltq_u32 (iax, d->tiny_bound));
+ /* Side-step special cases by setting those lanes to 0, which will trigger no
+ exceptions. These will be fixed up later. */
+ if (__glibc_unlikely (v_any_u32 (special)))
+ ax = v_zerofy_f32 (ax, special);
+#else
+ uint32x4_t special = vcgeq_u32 (iax, d->one);
+#endif
+
+ float32x4_t y = vdivq_f32 (vaddq_f32 (ax, ax), vsubq_f32 (v_f32 (1), ax));
+ y = log1pf_inline (y, d->log1pf_consts);
+
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return special_case (x, vmulq_f32 (halfsign, y), special);
+ return vmulq_f32 (halfsign, y);
+}
+libmvec_hidden_def (V_NAME_F1 (atanh))
+HALF_WIDTH_ALIAS_F1 (atanh)
diff --git a/sysdeps/aarch64/fpu/atanhf_sve.c b/sysdeps/aarch64/fpu/atanhf_sve.c
new file mode 100644
index 0000000000..dae83041ef
--- /dev/null
+++ b/sysdeps/aarch64/fpu/atanhf_sve.c
@@ -0,0 +1,54 @@
+/* Single-precision vector (SVE) atanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_log1pf_inline.h"
+
+#define One (0x3f800000)
+#define Half (0x3f000000)
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t special)
+{
+ return sv_call_f32 (atanhf, x, y, special);
+}
+
+/* Approximation for vector single-precision atanh(x) using modified log1p.
+ The maximum error is 2.28 ULP:
+ _ZGVsMxv_atanhf(0x1.ff1194p-5) got 0x1.ffbbbcp-5
+ want 0x1.ffbbb6p-5. */
+svfloat32_t SV_NAME_F1 (atanh) (svfloat32_t x, const svbool_t pg)
+{
+ svfloat32_t ax = svabs_x (pg, x);
+ svuint32_t iax = svreinterpret_u32 (ax);
+ svuint32_t sign = sveor_x (pg, svreinterpret_u32 (x), iax);
+ svfloat32_t halfsign = svreinterpret_f32 (svorr_x (pg, sign, Half));
+ svbool_t special = svcmpge (pg, iax, One);
+
+ /* Computation is performed based on the following sequence of equality:
+ * (1+x)/(1-x) = 1 + 2x/(1-x). */
+ svfloat32_t y = svadd_x (pg, ax, ax);
+ y = svdiv_x (pg, y, svsub_x (pg, sv_f32 (1), ax));
+ /* ln((1+x)/(1-x)) = ln(1+2x/(1-x)) = ln(1 + y). */
+ y = sv_log1pf_inline (y, pg);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svmul_x (pg, halfsign, y), special);
+
+ return svmul_x (pg, halfsign, y);
+}
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index eb2af35b27..ab7a8f7454 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -49,6 +49,10 @@
# define __DECL_SIMD_atan __DECL_SIMD_aarch64
# undef __DECL_SIMD_atanf
# define __DECL_SIMD_atanf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_atanh
+# define __DECL_SIMD_atanh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_atanhf
+# define __DECL_SIMD_atanhf __DECL_SIMD_aarch64
# undef __DECL_SIMD_atan2
# define __DECL_SIMD_atan2 __DECL_SIMD_aarch64
# undef __DECL_SIMD_atan2f
@@ -137,6 +141,7 @@ __vpcs __f32x4_t _ZGVnN4v_acoshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_asinhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_atanhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_erff (__f32x4_t);
@@ -157,6 +162,7 @@ __vpcs __f64x2_t _ZGVnN2v_acosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_asinh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_atan (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_atanh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_erf (__f64x2_t);
@@ -182,6 +188,7 @@ __sv_f32_t _ZGVsMxv_acoshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_asinhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_atanf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_atanhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_erff (__sv_f32_t, __sv_bool_t);
@@ -202,6 +209,7 @@ __sv_f64_t _ZGVsMxv_acosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_asinh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_atan (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_atanh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_erf (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index 3d7177c32d..a01aa99c16 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (acosh_advsimd, _ZGVnN2v_acosh)
VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
VPCS_VECTOR_WRAPPER (asinh_advsimd, _ZGVnN2v_asinh)
VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
+VPCS_VECTOR_WRAPPER (atanh_advsimd, _ZGVnN2v_atanh)
VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
VPCS_VECTOR_WRAPPER (cosh_advsimd, _ZGVnN2v_cosh)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index b88a2afe5c..83cb3ad5d0 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (acosh_sve, _ZGVsMxv_acosh)
SVE_VECTOR_WRAPPER (asin_sve, _ZGVsMxv_asin)
SVE_VECTOR_WRAPPER (asinh_sve, _ZGVsMxv_asinh)
SVE_VECTOR_WRAPPER (atan_sve, _ZGVsMxv_atan)
+SVE_VECTOR_WRAPPER (atanh_sve, _ZGVsMxv_atanh)
SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos)
SVE_VECTOR_WRAPPER (cosh_sve, _ZGVsMxv_cosh)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 533655402d..831d4d7552 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -28,6 +28,7 @@ VPCS_VECTOR_WRAPPER (acoshf_advsimd, _ZGVnN4v_acoshf)
VPCS_VECTOR_WRAPPER (asinf_advsimd, _ZGVnN4v_asinf)
VPCS_VECTOR_WRAPPER (asinhf_advsimd, _ZGVnN4v_asinhf)
VPCS_VECTOR_WRAPPER (atanf_advsimd, _ZGVnN4v_atanf)
+VPCS_VECTOR_WRAPPER (atanhf_advsimd, _ZGVnN4v_atanhf)
VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
VPCS_VECTOR_WRAPPER (coshf_advsimd, _ZGVnN4v_coshf)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index f7b673e335..96fd612c3e 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -47,6 +47,7 @@ SVE_VECTOR_WRAPPER (acoshf_sve, _ZGVsMxv_acoshf)
SVE_VECTOR_WRAPPER (asinf_sve, _ZGVsMxv_asinf)
SVE_VECTOR_WRAPPER (asinhf_sve, _ZGVsMxv_asinhf)
SVE_VECTOR_WRAPPER (atanf_sve, _ZGVsMxv_atanf)
+SVE_VECTOR_WRAPPER (atanhf_sve, _ZGVsMxv_atanhf)
SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf)
SVE_VECTOR_WRAPPER (coshf_sve, _ZGVsMxv_coshf)
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index dc8cb08b3a..e2b43107e5 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -173,11 +173,19 @@ double: 2
float: 2
ldouble: 4
+Function: "atanh_advsimd":
+double: 1
+float: 1
+
Function: "atanh_downward":
double: 3
float: 3
ldouble: 4
+Function: "atanh_sve":
+double: 2
+float: 1
+
Function: "atanh_towardzero":
double: 2
float: 2
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index f288afdfdd..ce42372a3a 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -77,18 +77,23 @@ GLIBC_2.40 _ZGVnN2v_acosh F
GLIBC_2.40 _ZGVnN2v_acoshf F
GLIBC_2.40 _ZGVnN2v_asinh F
GLIBC_2.40 _ZGVnN2v_asinhf F
+GLIBC_2.40 _ZGVnN2v_atanh F
+GLIBC_2.40 _ZGVnN2v_atanhf F
GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
GLIBC_2.40 _ZGVnN4v_acoshf F
GLIBC_2.40 _ZGVnN4v_asinhf F
+GLIBC_2.40 _ZGVnN4v_atanhf F
GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
GLIBC_2.40 _ZGVsMxv_acosh F
GLIBC_2.40 _ZGVsMxv_acoshf F
GLIBC_2.40 _ZGVsMxv_asinh F
GLIBC_2.40 _ZGVsMxv_asinhf F
+GLIBC_2.40 _ZGVsMxv_atanh F
+GLIBC_2.40 _ZGVsMxv_atanhf F
GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/8] aarch64/fpu: Add vector variants of sinh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
` (3 preceding siblings ...)
2024-02-20 16:59 ` [PATCH 5/8] aarch64/fpu: Add vector variants of atanh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:46 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 7/8] aarch64/fpu: Add vector variants of tanh Joe Ramsay
` (2 subsequent siblings)
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 1 +
sysdeps/aarch64/fpu/Versions | 15 ++-
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
sysdeps/aarch64/fpu/sinh_advsimd.c | 121 ++++++++++++++++++
sysdeps/aarch64/fpu/sinh_sve.c | 107 ++++++++++++++++
sysdeps/aarch64/fpu/sinhf_advsimd.c | 88 +++++++++++++
sysdeps/aarch64/fpu/sinhf_sve.c | 67 ++++++++++
sysdeps/aarch64/fpu/sv_expm1f_inline.h | 84 ++++++++++++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/fpu/v_expm1f_inline.h | 73 +++++++++++
sysdeps/aarch64/libm-test-ulps | 8 ++
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
16 files changed, 577 insertions(+), 5 deletions(-)
create mode 100644 sysdeps/aarch64/fpu/sinh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/sinh_sve.c
create mode 100644 sysdeps/aarch64/fpu/sinhf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/sinhf_sve.c
create mode 100644 sysdeps/aarch64/fpu/sv_expm1f_inline.h
create mode 100644 sysdeps/aarch64/fpu/v_expm1f_inline.h
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index 4c878e5906..fb5f3a365b 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -17,6 +17,7 @@ libmvec-supported-funcs = acos \
log1p \
log2 \
sin \
+ sinh \
tan
float-advsimd-funcs = $(libmvec-supported-funcs)
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 86c08c1fa3..4774b3efea 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -89,6 +89,11 @@ libmvec {
_ZGVnN4v_asinhf;
_ZGVsMxv_asinh;
_ZGVsMxv_asinhf;
+ _ZGVnN2v_atanh;
+ _ZGVnN2v_atanhf;
+ _ZGVnN4v_atanhf;
+ _ZGVsMxv_atanh;
+ _ZGVsMxv_atanhf;
_ZGVnN2v_cosh;
_ZGVnN2v_coshf;
_ZGVnN4v_coshf;
@@ -99,10 +104,10 @@ libmvec {
_ZGVnN4v_erff;
_ZGVsMxv_erf;
_ZGVsMxv_erff;
- _ZGVnN2v_atanh;
- _ZGVnN2v_atanhf;
- _ZGVnN4v_atanhf;
- _ZGVsMxv_atanh;
- _ZGVsMxv_atanhf;
+ _ZGVnN2v_sinh;
+ _ZGVnN2v_sinhf;
+ _ZGVnN4v_sinhf;
+ _ZGVsMxv_sinh;
+ _ZGVsMxv_sinhf;
}
}
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index afbb01e191..7d9445d5c0 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -35,5 +35,6 @@ libmvec_hidden_proto (V_NAME_F1(log1p));
libmvec_hidden_proto (V_NAME_F1(log2));
libmvec_hidden_proto (V_NAME_F1(log));
libmvec_hidden_proto (V_NAME_F1(sin));
+libmvec_hidden_proto (V_NAME_F1(sinh));
libmvec_hidden_proto (V_NAME_F1(tan));
libmvec_hidden_proto (V_NAME_F2(atan2));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index ab7a8f7454..1e9b76cf41 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -105,6 +105,10 @@
# define __DECL_SIMD_sin __DECL_SIMD_aarch64
# undef __DECL_SIMD_sinf
# define __DECL_SIMD_sinf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_sinh
+# define __DECL_SIMD_sinh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_sinhf
+# define __DECL_SIMD_sinhf __DECL_SIMD_aarch64
# undef __DECL_SIMD_tan
# define __DECL_SIMD_tan __DECL_SIMD_aarch64
# undef __DECL_SIMD_tanf
@@ -154,6 +158,7 @@ __vpcs __f32x4_t _ZGVnN4v_log10f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_log1pf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_log2f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_sinhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_tanf (__f32x4_t);
__vpcs __f64x2_t _ZGVnN2vv_atan2 (__f64x2_t, __f64x2_t);
@@ -175,6 +180,7 @@ __vpcs __f64x2_t _ZGVnN2v_log10 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_log1p (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_log2 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_sin (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_sinh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_tan (__f64x2_t);
# undef __ADVSIMD_VEC_MATH_SUPPORTED
@@ -201,6 +207,7 @@ __sv_f32_t _ZGVsMxv_log10f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_log1pf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_log2f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_sinf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_sinhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_tanf (__sv_f32_t, __sv_bool_t);
__sv_f64_t _ZGVsMxvv_atan2 (__sv_f64_t, __sv_f64_t, __sv_bool_t);
@@ -222,6 +229,7 @@ __sv_f64_t _ZGVsMxv_log10 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_log1p (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_log2 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_sin (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_sinh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_tan (__sv_f64_t, __sv_bool_t);
# undef __SVE_VEC_MATH_SUPPORTED
diff --git a/sysdeps/aarch64/fpu/sinh_advsimd.c b/sysdeps/aarch64/fpu/sinh_advsimd.c
new file mode 100644
index 0000000000..fa3723b10c
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sinh_advsimd.c
@@ -0,0 +1,121 @@
+/* Double-precision vector (Advanced SIMD) sinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "poly_advsimd_f64.h"
+
+static const struct data
+{
+ float64x2_t poly[11];
+ float64x2_t inv_ln2, m_ln2, shift;
+ uint64x2_t halff;
+ int64x2_t onef;
+#if WANT_SIMD_EXCEPT
+ uint64x2_t tiny_bound, thresh;
+#else
+ uint64x2_t large_bound;
+#endif
+} data = {
+ /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
+ .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
+ V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
+ V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
+ V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
+ V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
+
+ .inv_ln2 = V2 (0x1.71547652b82fep0),
+ .m_ln2 = (float64x2_t) {-0x1.62e42fefa39efp-1, -0x1.abc9e3b39803fp-56},
+ .shift = V2 (0x1.8p52),
+
+ .halff = V2 (0x3fe0000000000000),
+ .onef = V2 (0x3ff0000000000000),
+#if WANT_SIMD_EXCEPT
+ /* 2^-26, below which sinh(x) rounds to x. */
+ .tiny_bound = V2 (0x3e50000000000000),
+ /* asuint(large_bound) - asuint(tiny_bound). */
+ .thresh = V2 (0x0230000000000000),
+#else
+/* 2^9. expm1 helper overflows for large input. */
+ .large_bound = V2 (0x4080000000000000),
+#endif
+};
+
+static inline float64x2_t
+expm1_inline (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ /* Reduce argument:
+ exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
+ where i = round(x / ln2)
+ and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
+ float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
+ int64x2_t i = vcvtq_s64_f64 (j);
+ float64x2_t f = vfmaq_laneq_f64 (x, j, d->m_ln2, 0);
+ f = vfmaq_laneq_f64 (f, j, d->m_ln2, 1);
+ /* Approximate expm1(f) using polynomial. */
+ float64x2_t f2 = vmulq_f64 (f, f);
+ float64x2_t f4 = vmulq_f64 (f2, f2);
+ float64x2_t f8 = vmulq_f64 (f4, f4);
+ float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly));
+ /* t = 2^i. */
+ float64x2_t t = vreinterpretq_f64_u64 (
+ vreinterpretq_u64_s64 (vaddq_s64 (vshlq_n_s64 (i, 52), d->onef)));
+ /* expm1(x) ~= p * t + (t - 1). */
+ return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t);
+}
+
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x)
+{
+ return v_call_f64 (sinh, x, x, v_u64 (-1));
+}
+
+/* Approximation for vector double-precision sinh(x) using expm1.
+ sinh(x) = (exp(x) - exp(-x)) / 2.
+ The greatest observed error is 2.57 ULP:
+ _ZGVnN2v_sinh (0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
+ want 0x1.ab34e59d678d9p-2. */
+float64x2_t VPCS_ATTR V_NAME_D1 (sinh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ float64x2_t ax = vabsq_f64 (x);
+ uint64x2_t sign
+ = veorq_u64 (vreinterpretq_u64_f64 (x), vreinterpretq_u64_f64 (ax));
+ float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->halff));
+
+#if WANT_SIMD_EXCEPT
+ uint64x2_t special = vcgeq_u64 (
+ vsubq_u64 (vreinterpretq_u64_f64 (ax), d->tiny_bound), d->thresh);
+#else
+ uint64x2_t special = vcgeq_u64 (vreinterpretq_u64_f64 (ax), d->large_bound);
+#endif
+
+ /* Fall back to scalar variant for all lanes if any of them are special. */
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (x);
+
+ /* Up to the point that expm1 overflows, we can use it to calculate sinh
+ using a slight rearrangement of the definition of sinh. This allows us to
+ retain acceptable accuracy for very small inputs. */
+ float64x2_t t = expm1_inline (ax);
+ t = vaddq_f64 (t, vdivq_f64 (t, vaddq_f64 (t, v_f64 (1.0))));
+ return vmulq_f64 (t, halfsign);
+}
diff --git a/sysdeps/aarch64/fpu/sinh_sve.c b/sysdeps/aarch64/fpu/sinh_sve.c
new file mode 100644
index 0000000000..df5f6c8c06
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sinh_sve.c
@@ -0,0 +1,107 @@
+/* Double-precision vector (SVE) atanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "poly_sve_f64.h"
+
+static const struct data
+{
+ float64_t poly[11];
+ float64_t inv_ln2, m_ln2_hi, m_ln2_lo, shift;
+ uint64_t halff;
+ int64_t onef;
+ uint64_t large_bound;
+} data = {
+ /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
+ .poly = { 0x1p-1, 0x1.5555555555559p-3, 0x1.555555555554bp-5,
+ 0x1.111111110f663p-7, 0x1.6c16c16c1b5f3p-10,
+ 0x1.a01a01affa35dp-13, 0x1.a01a018b4ecbbp-16,
+ 0x1.71ddf82db5bb4p-19, 0x1.27e517fc0d54bp-22,
+ 0x1.af5eedae67435p-26, 0x1.1f143d060a28ap-29, },
+
+ .inv_ln2 = 0x1.71547652b82fep0,
+ .m_ln2_hi = -0x1.62e42fefa39efp-1,
+ .m_ln2_lo = -0x1.abc9e3b39803fp-56,
+ .shift = 0x1.8p52,
+
+ .halff = 0x3fe0000000000000,
+ .onef = 0x3ff0000000000000,
+ /* 2^9. expm1 helper overflows for large input. */
+ .large_bound = 0x4080000000000000,
+};
+
+static inline svfloat64_t
+expm1_inline (svfloat64_t x, svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ /* Reduce argument:
+ exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
+ where i = round(x / ln2)
+ and f = x - i * ln2 (f in [-ln2/2, ln2/2]). */
+ svfloat64_t j
+ = svsub_x (pg, svmla_x (pg, sv_f64 (d->shift), x, d->inv_ln2), d->shift);
+ svint64_t i = svcvt_s64_x (pg, j);
+ svfloat64_t f = svmla_x (pg, x, j, d->m_ln2_hi);
+ f = svmla_x (pg, f, j, d->m_ln2_lo);
+ /* Approximate expm1(f) using polynomial. */
+ svfloat64_t f2 = svmul_x (pg, f, f);
+ svfloat64_t f4 = svmul_x (pg, f2, f2);
+ svfloat64_t f8 = svmul_x (pg, f4, f4);
+ svfloat64_t p
+ = svmla_x (pg, f, f2, sv_estrin_10_f64_x (pg, f, f2, f4, f8, d->poly));
+ /* t = 2^i. */
+ svfloat64_t t = svscale_x (pg, sv_f64 (1), i);
+ /* expm1(x) ~= p * t + (t - 1). */
+ return svmla_x (pg, svsub_x (pg, t, 1.0), p, t);
+}
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svbool_t pg)
+{
+ return sv_call_f64 (sinh, x, x, pg);
+}
+
+/* Approximation for SVE double-precision sinh(x) using expm1.
+ sinh(x) = (exp(x) - exp(-x)) / 2.
+ The greatest observed error is 2.57 ULP:
+ _ZGVsMxv_sinh (0x1.a008538399931p-2) got 0x1.ab929fc64bd66p-2
+ want 0x1.ab929fc64bd63p-2. */
+svfloat64_t SV_NAME_D1 (sinh) (svfloat64_t x, svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svfloat64_t ax = svabs_x (pg, x);
+ svuint64_t sign
+ = sveor_x (pg, svreinterpret_u64 (x), svreinterpret_u64 (ax));
+ svfloat64_t halfsign = svreinterpret_f64 (svorr_x (pg, sign, d->halff));
+
+ svbool_t special = svcmpge (pg, svreinterpret_u64 (ax), d->large_bound);
+
+ /* Fall back to scalar variant for all lanes if any are special. */
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, pg);
+
+ /* Up to the point that expm1 overflows, we can use it to calculate sinh
+ using a slight rearrangement of the definition of sinh. This allows us to
+ retain acceptable accuracy for very small inputs. */
+ svfloat64_t t = expm1_inline (ax, pg);
+ t = svadd_x (pg, t, svdiv_x (pg, t, svadd_x (pg, t, 1.0)));
+ return svmul_x (pg, t, halfsign);
+}
diff --git a/sysdeps/aarch64/fpu/sinhf_advsimd.c b/sysdeps/aarch64/fpu/sinhf_advsimd.c
new file mode 100644
index 0000000000..6bb7482dc2
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sinhf_advsimd.c
@@ -0,0 +1,88 @@
+/* Single-precision vector (Advanced SIMD) sinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "v_expm1f_inline.h"
+
+static const struct data
+{
+ struct v_expm1f_data expm1f_consts;
+ uint32x4_t halff;
+#if WANT_SIMD_EXCEPT
+ uint32x4_t tiny_bound, thresh;
+#else
+ uint32x4_t oflow_bound;
+#endif
+} data = {
+ .expm1f_consts = V_EXPM1F_DATA,
+ .halff = V4 (0x3f000000),
+#if WANT_SIMD_EXCEPT
+ /* 0x1.6a09e8p-32, below which expm1f underflows. */
+ .tiny_bound = V4 (0x2fb504f4),
+ /* asuint(oflow_bound) - asuint(tiny_bound). */
+ .thresh = V4 (0x12fbbbb3),
+#else
+ /* 0x1.61814ep+6, above which expm1f helper overflows. */
+ .oflow_bound = V4 (0x42b0c0a7),
+#endif
+};
+
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
+{
+ return v_call_f32 (sinhf, x, y, special);
+}
+
+/* Approximation for vector single-precision sinh(x) using expm1.
+ sinh(x) = (exp(x) - exp(-x)) / 2.
+ The maximum error is 2.26 ULP:
+ _ZGVnN4v_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4
+ want 0x1.e469e4p-4. */
+float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (sinh) (float32x4_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ uint32x4_t ix = vreinterpretq_u32_f32 (x);
+ float32x4_t ax = vabsq_f32 (x);
+ uint32x4_t iax = vreinterpretq_u32_f32 (ax);
+ uint32x4_t sign = veorq_u32 (ix, iax);
+ float32x4_t halfsign = vreinterpretq_f32_u32 (vorrq_u32 (sign, d->halff));
+
+#if WANT_SIMD_EXCEPT
+ uint32x4_t special = vcgeq_u32 (vsubq_u32 (iax, d->tiny_bound), d->thresh);
+ ax = v_zerofy_f32 (ax, special);
+#else
+ uint32x4_t special = vcgeq_u32 (iax, d->oflow_bound);
+#endif
+
+ /* Up to the point that expm1f overflows, we can use it to calculate sinhf
+ using a slight rearrangement of the definition of asinh. This allows us
+ to retain acceptable accuracy for very small inputs. */
+ float32x4_t t = expm1f_inline (ax, &d->expm1f_consts);
+ t = vaddq_f32 (t, vdivq_f32 (t, vaddq_f32 (t, v_f32 (1.0))));
+
+ /* Fall back to the scalar variant for any lanes that should trigger an
+ exception. */
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return special_case (x, vmulq_f32 (t, halfsign), special);
+
+ return vmulq_f32 (t, halfsign);
+}
+libmvec_hidden_def (V_NAME_F1 (sinh))
+HALF_WIDTH_ALIAS_F1 (sinh)
diff --git a/sysdeps/aarch64/fpu/sinhf_sve.c b/sysdeps/aarch64/fpu/sinhf_sve.c
new file mode 100644
index 0000000000..6c204b57a2
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sinhf_sve.c
@@ -0,0 +1,67 @@
+/* Single-precision vector (SVE) sinh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_expm1f_inline.h"
+#include "sv_math.h"
+
+static const struct data
+{
+ struct sv_expm1f_data expm1f_consts;
+ uint32_t halff, large_bound;
+} data = {
+ .expm1f_consts = SV_EXPM1F_DATA,
+ .halff = 0x3f000000,
+ /* 0x1.61814ep+6, above which expm1f helper overflows. */
+ .large_bound = 0x42b0c0a7,
+};
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t pg)
+{
+ return sv_call_f32 (sinhf, x, y, pg);
+}
+
+/* Approximation for SVE single-precision sinh(x) using expm1.
+ sinh(x) = (exp(x) - exp(-x)) / 2.
+ The maximum error is 2.26 ULP:
+ _ZGVsMxv_sinhf (0x1.e34a9ep-4) got 0x1.e469ep-4
+ want 0x1.e469e4p-4. */
+svfloat32_t SV_NAME_F1 (sinh) (svfloat32_t x, const svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+ svfloat32_t ax = svabs_x (pg, x);
+ svuint32_t sign
+ = sveor_x (pg, svreinterpret_u32 (x), svreinterpret_u32 (ax));
+ svfloat32_t halfsign = svreinterpret_f32 (svorr_x (pg, sign, d->halff));
+
+ svbool_t special = svcmpge (pg, svreinterpret_u32 (ax), d->large_bound);
+
+ /* Up to the point that expm1f overflows, we can use it to calculate sinhf
+ using a slight rearrangement of the definition of asinh. This allows us to
+ retain acceptable accuracy for very small inputs. */
+ svfloat32_t t = expm1f_inline (ax, pg, &d->expm1f_consts);
+ t = svadd_x (pg, t, svdiv_x (pg, t, svadd_x (pg, t, 1.0)));
+
+ /* Fall back to the scalar variant for any lanes which would cause
+ expm1f to overflow. */
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svmul_x (pg, t, halfsign), special);
+
+ return svmul_x (pg, t, halfsign);
+}
diff --git a/sysdeps/aarch64/fpu/sv_expm1f_inline.h b/sysdeps/aarch64/fpu/sv_expm1f_inline.h
new file mode 100644
index 0000000000..5b72451222
--- /dev/null
+++ b/sysdeps/aarch64/fpu/sv_expm1f_inline.h
@@ -0,0 +1,84 @@
+/* Single-precision inline helper for vector (SVE) expm1 function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_SV_EXPM1F_INLINE_H
+#define AARCH64_FPU_SV_EXPM1F_INLINE_H
+
+#include "sv_math.h"
+
+struct sv_expm1f_data
+{
+ /* These 4 are grouped together so they can be loaded as one quadword, then
+ used with _lane forms of svmla/svmls. */
+ float32_t c2, c4, ln2_hi, ln2_lo;
+ float32_t c0, c1, c3, inv_ln2, shift;
+};
+
+/* Coefficients generated using fpminimax. */
+#define SV_EXPM1F_DATA \
+ { \
+ .c0 = 0x1.fffffep-2, .c1 = 0x1.5554aep-3, .c2 = 0x1.555736p-5, \
+ .c3 = 0x1.12287cp-7, .c4 = 0x1.6b55a2p-10, \
+ \
+ .shift = 0x1.8p23f, .inv_ln2 = 0x1.715476p+0f, .ln2_hi = 0x1.62e4p-1f, \
+ .ln2_lo = 0x1.7f7d1cp-20f, \
+ }
+
+#define C(i) sv_f32 (d->c##i)
+
+static inline svfloat32_t
+expm1f_inline (svfloat32_t x, svbool_t pg, const struct sv_expm1f_data *d)
+{
+ /* This vector is reliant on layout of data - it contains constants
+ that can be used with _lane forms of svmla/svmls. Values are:
+ [ coeff_2, coeff_4, ln2_hi, ln2_lo ]. */
+ svfloat32_t lane_constants = svld1rq (svptrue_b32 (), &d->c2);
+
+ /* Reduce argument to smaller range:
+ Let i = round(x / ln2)
+ and f = x - i * ln2, then f is in [-ln2/2, ln2/2].
+ exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
+ where 2^i is exact because i is an integer. */
+ svfloat32_t j = svmla_x (pg, sv_f32 (d->shift), x, d->inv_ln2);
+ j = svsub_x (pg, j, d->shift);
+ svint32_t i = svcvt_s32_x (pg, j);
+
+ svfloat32_t f = svmls_lane (x, j, lane_constants, 2);
+ f = svmls_lane (f, j, lane_constants, 3);
+
+ /* Approximate expm1(f) using polynomial.
+ Taylor expansion for expm1(x) has the form:
+ x + ax^2 + bx^3 + cx^4 ....
+ So we calculate the polynomial P(f) = a + bf + cf^2 + ...
+ and assemble the approximation expm1(f) ~= f + f^2 * P(f). */
+ svfloat32_t p12 = svmla_lane (C (1), f, lane_constants, 0);
+ svfloat32_t p34 = svmla_lane (C (3), f, lane_constants, 1);
+ svfloat32_t f2 = svmul_x (pg, f, f);
+ svfloat32_t p = svmla_x (pg, p12, f2, p34);
+ p = svmla_x (pg, C (0), f, p);
+ p = svmla_x (pg, f, f2, p);
+
+ /* Assemble the result.
+ expm1(x) ~= 2^i * (p + 1) - 1
+ Let t = 2^i. */
+ svfloat32_t t = svscale_x (pg, sv_f32 (1), i);
+ return svmla_x (pg, svsub_x (pg, t, 1), p, t);
+}
+
+#endif
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index a01aa99c16..1a57b22c3a 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -42,4 +42,5 @@ VPCS_VECTOR_WRAPPER (log10_advsimd, _ZGVnN2v_log10)
VPCS_VECTOR_WRAPPER (log1p_advsimd, _ZGVnN2v_log1p)
VPCS_VECTOR_WRAPPER (log2_advsimd, _ZGVnN2v_log2)
VPCS_VECTOR_WRAPPER (sin_advsimd, _ZGVnN2v_sin)
+VPCS_VECTOR_WRAPPER (sinh_advsimd, _ZGVnN2v_sinh)
VPCS_VECTOR_WRAPPER (tan_advsimd, _ZGVnN2v_tan)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 83cb3ad5d0..0c9858f6b7 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -61,4 +61,5 @@ SVE_VECTOR_WRAPPER (log10_sve, _ZGVsMxv_log10)
SVE_VECTOR_WRAPPER (log1p_sve, _ZGVsMxv_log1p)
SVE_VECTOR_WRAPPER (log2_sve, _ZGVsMxv_log2)
SVE_VECTOR_WRAPPER (sin_sve, _ZGVsMxv_sin)
+SVE_VECTOR_WRAPPER (sinh_sve, _ZGVsMxv_sinh)
SVE_VECTOR_WRAPPER (tan_sve, _ZGVsMxv_tan)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 831d4d7552..4758490c6f 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -42,4 +42,5 @@ VPCS_VECTOR_WRAPPER (log10f_advsimd, _ZGVnN4v_log10f)
VPCS_VECTOR_WRAPPER (log1pf_advsimd, _ZGVnN4v_log1pf)
VPCS_VECTOR_WRAPPER (log2f_advsimd, _ZGVnN4v_log2f)
VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf)
+VPCS_VECTOR_WRAPPER (sinhf_advsimd, _ZGVnN4v_sinhf)
VPCS_VECTOR_WRAPPER (tanf_advsimd, _ZGVnN4v_tanf)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index 96fd612c3e..7c04f07bbe 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -61,4 +61,5 @@ SVE_VECTOR_WRAPPER (log10f_sve, _ZGVsMxv_log10f)
SVE_VECTOR_WRAPPER (log1pf_sve, _ZGVsMxv_log1pf)
SVE_VECTOR_WRAPPER (log2f_sve, _ZGVsMxv_log2f)
SVE_VECTOR_WRAPPER (sinf_sve, _ZGVsMxv_sinf)
+SVE_VECTOR_WRAPPER (sinhf_sve, _ZGVsMxv_sinhf)
SVE_VECTOR_WRAPPER (tanf_sve, _ZGVsMxv_tanf)
diff --git a/sysdeps/aarch64/fpu/v_expm1f_inline.h b/sysdeps/aarch64/fpu/v_expm1f_inline.h
new file mode 100644
index 0000000000..337ccfbfab
--- /dev/null
+++ b/sysdeps/aarch64/fpu/v_expm1f_inline.h
@@ -0,0 +1,73 @@
+/* Single-precision inline helper for vector (Advanced SIMD) expm1 function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#ifndef AARCH64_FPU_V_EXPM1F_INLINE_H
+#define AARCH64_FPU_V_EXPM1F_INLINE_H
+
+#include "v_math.h"
+#include "poly_advsimd_f32.h"
+
+struct v_expm1f_data
+{
+ float32x4_t poly[5];
+ float32x4_t invln2_and_ln2, shift;
+ int32x4_t exponent_bias;
+};
+
+/* Coefficients generated using fpminimax with degree=5 in [-log(2)/2,
+ log(2)/2]. Exponent bias is asuint(1.0f).
+ invln2_and_ln2 Stores constants: invln2, ln2_lo, ln2_hi, 0. */
+#define V_EXPM1F_DATA \
+ { \
+ .poly = { V4 (0x1.fffffep-2), V4 (0x1.5554aep-3), V4 (0x1.555736p-5), \
+ V4 (0x1.12287cp-7), V4 (0x1.6b55a2p-10) }, \
+ .shift = V4 (0x1.8p23f), .exponent_bias = V4 (0x3f800000), \
+ .invln2_and_ln2 = { 0x1.715476p+0f, 0x1.62e4p-1f, 0x1.7f7d1cp-20f, 0 }, \
+ }
+
+static inline float32x4_t
+expm1f_inline (float32x4_t x, const struct v_expm1f_data *d)
+{
+ /* Helper routine for calculating exp(x) - 1.
+ Copied from v_expm1f_1u6.c, with all special-case handling removed - the
+ calling routine should handle special values if required. */
+
+ /* Reduce argument: f in [-ln2/2, ln2/2], i is exact. */
+ float32x4_t j = vsubq_f32 (
+ vfmaq_laneq_f32 (d->shift, x, d->invln2_and_ln2, 0), d->shift);
+ int32x4_t i = vcvtq_s32_f32 (j);
+ float32x4_t f = vfmsq_laneq_f32 (x, j, d->invln2_and_ln2, 1);
+ f = vfmsq_laneq_f32 (f, j, d->invln2_and_ln2, 2);
+
+ /* Approximate expm1(f) with polynomial P, expm1(f) ~= f + f^2 * P(f).
+ Uses Estrin scheme, where the main _ZGVnN4v_expm1f routine uses
+ Horner. */
+ float32x4_t f2 = vmulq_f32 (f, f);
+ float32x4_t f4 = vmulq_f32 (f2, f2);
+ float32x4_t p = v_estrin_4_f32 (f, f2, f4, d->poly);
+ p = vfmaq_f32 (f, f2, p);
+
+ /* t = 2^i. */
+ int32x4_t u = vaddq_s32 (vshlq_n_s32 (i, 23), d->exponent_bias);
+ float32x4_t t = vreinterpretq_f32_s32 (u);
+ /* expm1(x) ~= p * t + (t - 1). */
+ return vfmaq_f32 (vsubq_f32 (t, v_f32 (1.0f)), p, t);
+}
+
+#endif
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index e2b43107e5..004eb34694 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -1441,11 +1441,19 @@ double: 2
float: 2
ldouble: 2
+Function: "sinh_advsimd":
+double: 2
+float: 1
+
Function: "sinh_downward":
double: 3
float: 3
ldouble: 3
+Function: "sinh_sve":
+double: 2
+float: 1
+
Function: "sinh_towardzero":
double: 3
float: 2
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index ce42372a3a..1db5ba61d6 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -83,11 +83,14 @@ GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
+GLIBC_2.40 _ZGVnN2v_sinh F
+GLIBC_2.40 _ZGVnN2v_sinhf F
GLIBC_2.40 _ZGVnN4v_acoshf F
GLIBC_2.40 _ZGVnN4v_asinhf F
GLIBC_2.40 _ZGVnN4v_atanhf F
GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
+GLIBC_2.40 _ZGVnN4v_sinhf F
GLIBC_2.40 _ZGVsMxv_acosh F
GLIBC_2.40 _ZGVsMxv_acoshf F
GLIBC_2.40 _ZGVsMxv_asinh F
@@ -98,3 +101,5 @@ GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
GLIBC_2.40 _ZGVsMxv_erff F
+GLIBC_2.40 _ZGVsMxv_sinh F
+GLIBC_2.40 _ZGVsMxv_sinhf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 7/8] aarch64/fpu: Add vector variants of tanh
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
` (4 preceding siblings ...)
2024-02-20 16:59 ` [PATCH 6/8] aarch64/fpu: Add vector variants of sinh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:51 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 8/8] aarch64/fpu: Add vector variants of erfc Joe Ramsay
2024-03-21 14:37 ` [PATCH 1/8] aarch64/fpu: Add vector variants of erf Szabolcs Nagy
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
math/auto-libm-test-in | 2 +-
math/auto-libm-test-out-tanh | 50 ++++----
sysdeps/aarch64/fpu/Makefile | 3 +-
sysdeps/aarch64/fpu/Versions | 5 +
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
sysdeps/aarch64/fpu/tanh_advsimd.c | 109 ++++++++++++++++++
sysdeps/aarch64/fpu/tanh_sve.c | 100 ++++++++++++++++
sysdeps/aarch64/fpu/tanhf_advsimd.c | 76 ++++++++++++
sysdeps/aarch64/fpu/tanhf_sve.c | 61 ++++++++++
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/libm-test-ulps | 8 ++
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
16 files changed, 405 insertions(+), 27 deletions(-)
create mode 100644 sysdeps/aarch64/fpu/tanh_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/tanh_sve.c
create mode 100644 sysdeps/aarch64/fpu/tanhf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/tanhf_sve.c
diff --git a/math/auto-libm-test-in b/math/auto-libm-test-in
index d728f97770..05d7ae5002 100644
--- a/math/auto-libm-test-in
+++ b/math/auto-libm-test-in
@@ -7747,7 +7747,7 @@ tan min_subnorm
tan -min_subnorm
tanh 0
-tanh -0
+tanh -0 no-mathvec
tanh 0.75
tanh -0.75
tanh 1.0
diff --git a/math/auto-libm-test-out-tanh b/math/auto-libm-test-out-tanh
index 8b9427c917..19ce2e7b93 100644
--- a/math/auto-libm-test-out-tanh
+++ b/math/auto-libm-test-out-tanh
@@ -23,31 +23,31 @@ tanh 0
= tanh tonearest ibm128 0x0p+0 : 0x0p+0 : inexact-ok
= tanh towardzero ibm128 0x0p+0 : 0x0p+0 : inexact-ok
= tanh upward ibm128 0x0p+0 : 0x0p+0 : inexact-ok
-tanh -0
-= tanh downward binary32 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest binary32 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero binary32 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward binary32 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh downward binary64 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest binary64 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero binary64 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward binary64 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh downward intel96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest intel96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero intel96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward intel96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh downward m68k96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest m68k96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero m68k96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward m68k96 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh downward binary128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest binary128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero binary128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward binary128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh downward ibm128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh tonearest ibm128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh towardzero ibm128 -0x0p+0 : -0x0p+0 : inexact-ok
-= tanh upward ibm128 -0x0p+0 : -0x0p+0 : inexact-ok
+tanh -0 no-mathvec
+= tanh downward binary32 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest binary32 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero binary32 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward binary32 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh downward binary64 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest binary64 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero binary64 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward binary64 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh downward intel96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest intel96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero intel96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward intel96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh downward m68k96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest m68k96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero m68k96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward m68k96 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh downward binary128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest binary128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero binary128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward binary128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh downward ibm128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh tonearest ibm128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh towardzero ibm128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
+= tanh upward ibm128 -0x0p+0 : -0x0p+0 : no-mathvec inexact-ok
tanh 0.75
= tanh downward binary32 0xcp-4 : 0xa.2991fp-4 : inexact-ok
= tanh tonearest binary32 0xcp-4 : 0xa.2991fp-4 : inexact-ok
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index fb5f3a365b..e5f418ae42 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -18,7 +18,8 @@ libmvec-supported-funcs = acos \
log2 \
sin \
sinh \
- tan
+ tan \
+ tanh
float-advsimd-funcs = $(libmvec-supported-funcs)
double-advsimd-funcs = $(libmvec-supported-funcs)
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 4774b3efea..4dbf3d3244 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -109,5 +109,10 @@ libmvec {
_ZGVnN4v_sinhf;
_ZGVsMxv_sinh;
_ZGVsMxv_sinhf;
+ _ZGVnN2v_tanh;
+ _ZGVnN2v_tanhf;
+ _ZGVnN4v_tanhf;
+ _ZGVsMxv_tanh;
+ _ZGVsMxv_tanhf;
}
}
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index 7d9445d5c0..4ff191c324 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -37,4 +37,5 @@ libmvec_hidden_proto (V_NAME_F1(log));
libmvec_hidden_proto (V_NAME_F1(sin));
libmvec_hidden_proto (V_NAME_F1(sinh));
libmvec_hidden_proto (V_NAME_F1(tan));
+libmvec_hidden_proto (V_NAME_F1(tanh));
libmvec_hidden_proto (V_NAME_F2(atan2));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 1e9b76cf41..585e022082 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -113,6 +113,10 @@
# define __DECL_SIMD_tan __DECL_SIMD_aarch64
# undef __DECL_SIMD_tanf
# define __DECL_SIMD_tanf __DECL_SIMD_aarch64
+# undef __DECL_SIMD_tanh
+# define __DECL_SIMD_tanh __DECL_SIMD_aarch64
+# undef __DECL_SIMD_tanhf
+# define __DECL_SIMD_tanhf __DECL_SIMD_aarch64
#endif
#if __GNUC_PREREQ(9, 0)
@@ -160,6 +164,7 @@ __vpcs __f32x4_t _ZGVnN4v_log2f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_sinf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_sinhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_tanf (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_tanhf (__f32x4_t);
__vpcs __f64x2_t _ZGVnN2vv_atan2 (__f64x2_t, __f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_acos (__f64x2_t);
@@ -182,6 +187,7 @@ __vpcs __f64x2_t _ZGVnN2v_log2 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_sin (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_sinh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_tan (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_tanh (__f64x2_t);
# undef __ADVSIMD_VEC_MATH_SUPPORTED
#endif /* __ADVSIMD_VEC_MATH_SUPPORTED */
@@ -209,6 +215,7 @@ __sv_f32_t _ZGVsMxv_log2f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_sinf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_sinhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_tanf (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_tanhf (__sv_f32_t, __sv_bool_t);
__sv_f64_t _ZGVsMxvv_atan2 (__sv_f64_t, __sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_acos (__sv_f64_t, __sv_bool_t);
@@ -231,6 +238,7 @@ __sv_f64_t _ZGVsMxv_log2 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_sin (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_sinh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_tan (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_tanh (__sv_f64_t, __sv_bool_t);
# undef __SVE_VEC_MATH_SUPPORTED
#endif /* __SVE_VEC_MATH_SUPPORTED */
diff --git a/sysdeps/aarch64/fpu/tanh_advsimd.c b/sysdeps/aarch64/fpu/tanh_advsimd.c
new file mode 100644
index 0000000000..1da1dfa5db
--- /dev/null
+++ b/sysdeps/aarch64/fpu/tanh_advsimd.c
@@ -0,0 +1,109 @@
+/* Double-precision vector (Advanced SIMD) tanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "poly_advsimd_f64.h"
+
+static const struct data
+{
+ float64x2_t poly[11];
+ float64x2_t inv_ln2, ln2_hi, ln2_lo, shift;
+ uint64x2_t onef;
+ uint64x2_t thresh, tiny_bound;
+} data = {
+ /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
+ .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
+ V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
+ V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
+ V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
+ V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
+
+ .inv_ln2 = V2 (0x1.71547652b82fep0),
+ .ln2_hi = V2 (-0x1.62e42fefa39efp-1),
+ .ln2_lo = V2 (-0x1.abc9e3b39803fp-56),
+ .shift = V2 (0x1.8p52),
+
+ .onef = V2 (0x3ff0000000000000),
+ .tiny_bound = V2 (0x3e40000000000000), /* asuint64 (0x1p-27). */
+ /* asuint64(0x1.241bf835f9d5fp+4) - asuint64(tiny_bound). */
+ .thresh = V2 (0x01f241bf835f9d5f),
+};
+
+static inline float64x2_t
+expm1_inline (float64x2_t x, const struct data *d)
+{
+ /* Helper routine for calculating exp(x) - 1. Vector port of the helper from
+ the scalar variant of tanh. */
+
+ /* Reduce argument: f in [-ln2/2, ln2/2], i is exact. */
+ float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
+ int64x2_t i = vcvtq_s64_f64 (j);
+ float64x2_t f = vfmaq_f64 (x, j, d->ln2_hi);
+ f = vfmaq_f64 (f, j, d->ln2_lo);
+
+ /* Approximate expm1(f) using polynomial. */
+ float64x2_t f2 = vmulq_f64 (f, f);
+ float64x2_t f4 = vmulq_f64 (f2, f2);
+ float64x2_t p = vfmaq_f64 (
+ f, f2, v_estrin_10_f64 (f, f2, f4, vmulq_f64 (f4, f4), d->poly));
+
+ /* t = 2 ^ i. */
+ float64x2_t t = vreinterpretq_f64_u64 (
+ vaddq_u64 (vreinterpretq_u64_s64 (i << 52), d->onef));
+ /* expm1(x) = p * t + (t - 1). */
+ return vfmaq_f64 (vsubq_f64 (t, v_f64 (1)), p, t);
+}
+
+static float64x2_t NOINLINE VPCS_ATTR
+special_case (float64x2_t x, float64x2_t y, uint64x2_t special)
+{
+ return v_call_f64 (tanh, x, y, special);
+}
+
+/* Vector approximation for double-precision tanh(x), using a simplified
+ version of expm1. The greatest observed error is 2.77 ULP:
+ _ZGVnN2v_tanh(-0x1.c4a4ca0f9f3b7p-3) got -0x1.bd6a21a163627p-3
+ want -0x1.bd6a21a163624p-3. */
+float64x2_t VPCS_ATTR V_NAME_D1 (tanh) (float64x2_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ uint64x2_t ia = vreinterpretq_u64_f64 (vabsq_f64 (x));
+
+ float64x2_t u = x;
+
+ /* Trigger special-cases for tiny, boring and infinity/NaN. */
+ uint64x2_t special = vcgtq_u64 (vsubq_u64 (ia, d->tiny_bound), d->thresh);
+#if WANT_SIMD_EXCEPT
+ /* To trigger fp exceptions correctly, set special lanes to a neutral value.
+ They will be fixed up later by the special-case handler. */
+ if (__glibc_unlikely (v_any_u64 (special)))
+ u = v_zerofy_f64 (u, special);
+#endif
+
+ u = vaddq_f64 (u, u);
+
+ /* tanh(x) = (e^2x - 1) / (e^2x + 1). */
+ float64x2_t q = expm1_inline (u, d);
+ float64x2_t qp2 = vaddq_f64 (q, v_f64 (2));
+
+ if (__glibc_unlikely (v_any_u64 (special)))
+ return special_case (x, vdivq_f64 (q, qp2), special);
+ return vdivq_f64 (q, qp2);
+}
diff --git a/sysdeps/aarch64/fpu/tanh_sve.c b/sysdeps/aarch64/fpu/tanh_sve.c
new file mode 100644
index 0000000000..d25e011cea
--- /dev/null
+++ b/sysdeps/aarch64/fpu/tanh_sve.c
@@ -0,0 +1,100 @@
+/* Double-precision vector (SVE) tanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "poly_sve_f64.h"
+
+static const struct data
+{
+ float64_t poly[11];
+ float64_t inv_ln2, ln2_hi, ln2_lo, shift;
+ uint64_t thresh, tiny_bound;
+} data = {
+ /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2]. */
+ .poly = { 0x1p-1, 0x1.5555555555559p-3, 0x1.555555555554bp-5,
+ 0x1.111111110f663p-7, 0x1.6c16c16c1b5f3p-10,
+ 0x1.a01a01affa35dp-13, 0x1.a01a018b4ecbbp-16,
+ 0x1.71ddf82db5bb4p-19, 0x1.27e517fc0d54bp-22,
+ 0x1.af5eedae67435p-26, 0x1.1f143d060a28ap-29, },
+
+ .inv_ln2 = 0x1.71547652b82fep0,
+ .ln2_hi = -0x1.62e42fefa39efp-1,
+ .ln2_lo = -0x1.abc9e3b39803fp-56,
+ .shift = 0x1.8p52,
+
+ .tiny_bound = 0x3e40000000000000, /* asuint64 (0x1p-27). */
+ /* asuint64(0x1.241bf835f9d5fp+4) - asuint64(tiny_bound). */
+ .thresh = 0x01f241bf835f9d5f,
+};
+
+static inline svfloat64_t
+expm1_inline (svfloat64_t x, const svbool_t pg, const struct data *d)
+{
+ /* Helper routine for calculating exp(x) - 1. Vector port of the helper from
+ the scalar variant of tanh. */
+
+ /* Reduce argument: f in [-ln2/2, ln2/2], i is exact. */
+ svfloat64_t j
+ = svsub_x (pg, svmla_x (pg, sv_f64 (d->shift), x, d->inv_ln2), d->shift);
+ svint64_t i = svcvt_s64_x (pg, j);
+ svfloat64_t f = svmla_x (pg, x, j, d->ln2_hi);
+ f = svmla_x (pg, f, j, d->ln2_lo);
+
+ /* Approximate expm1(f) using polynomial. */
+ svfloat64_t f2 = svmul_x (pg, f, f);
+ svfloat64_t f4 = svmul_x (pg, f2, f2);
+ svfloat64_t p = svmla_x (
+ pg, f, f2,
+ sv_estrin_10_f64_x (pg, f, f2, f4, svmul_x (pg, f4, f4), d->poly));
+
+ /* t = 2 ^ i. */
+ svfloat64_t t = svscale_x (pg, sv_f64 (1), i);
+ /* expm1(x) = p * t + (t - 1). */
+ return svmla_x (pg, svsub_x (pg, t, 1), p, t);
+}
+
+static svfloat64_t NOINLINE
+special_case (svfloat64_t x, svfloat64_t y, svbool_t special)
+{
+ return sv_call_f64 (tanh, x, y, special);
+}
+
+/* SVE approximation for double-precision tanh(x), using a simplified
+ version of expm1. The greatest observed error is 2.77 ULP:
+ _ZGVsMxv_tanh(-0x1.c4a4ca0f9f3b7p-3) got -0x1.bd6a21a163627p-3
+ want -0x1.bd6a21a163624p-3. */
+svfloat64_t SV_NAME_D1 (tanh) (svfloat64_t x, svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svuint64_t ia = svreinterpret_u64 (svabs_x (pg, x));
+
+ /* Trigger special-cases for tiny, boring and infinity/NaN. */
+ svbool_t special = svcmpgt (pg, svsub_x (pg, ia, d->tiny_bound), d->thresh);
+
+ svfloat64_t u = svadd_x (pg, x, x);
+
+ /* tanh(x) = (e^2x - 1) / (e^2x + 1). */
+ svfloat64_t q = expm1_inline (u, pg, d);
+ svfloat64_t qp2 = svadd_x (pg, q, 2);
+
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svdiv_x (pg, q, qp2), special);
+ return svdiv_x (pg, q, qp2);
+}
diff --git a/sysdeps/aarch64/fpu/tanhf_advsimd.c b/sysdeps/aarch64/fpu/tanhf_advsimd.c
new file mode 100644
index 0000000000..50defd6ef0
--- /dev/null
+++ b/sysdeps/aarch64/fpu/tanhf_advsimd.c
@@ -0,0 +1,76 @@
+/* Single-precision vector (Advanced SIMD) tanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_expm1f_inline.h"
+
+static const struct data
+{
+ struct v_expm1f_data expm1f_consts;
+ uint32x4_t boring_bound, large_bound, onef;
+} data = {
+ .expm1f_consts = V_EXPM1F_DATA,
+ /* 0x1.205966p+3, above which tanhf rounds to 1 (or -1 for negative). */
+ .boring_bound = V4 (0x41102cb3),
+ .large_bound = V4 (0x7f800000),
+ .onef = V4 (0x3f800000),
+};
+
+static float32x4_t NOINLINE VPCS_ATTR
+special_case (float32x4_t x, float32x4_t y, uint32x4_t special)
+{
+ return v_call_f32 (tanhf, x, y, special);
+}
+
+/* Approximation for single-precision vector tanh(x), using a simplified
+ version of expm1f. The maximum error is 2.58 ULP:
+ _ZGVnN4v_tanhf (0x1.fa5eep-5) got 0x1.f9ba02p-5
+ want 0x1.f9ba08p-5. */
+float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (tanh) (float32x4_t x)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ uint32x4_t ix = vreinterpretq_u32_f32 (x);
+ float32x4_t ax = vabsq_f32 (x);
+ uint32x4_t iax = vreinterpretq_u32_f32 (ax);
+ uint32x4_t sign = veorq_u32 (ix, iax);
+ uint32x4_t is_boring = vcgtq_u32 (iax, d->boring_bound);
+ float32x4_t boring = vreinterpretq_f32_u32 (vorrq_u32 (sign, d->onef));
+
+#if WANT_SIMD_EXCEPT
+ /* If fp exceptions are to be triggered properly, set all special and boring
+ lanes to 0, which will trigger no exceptions, and fix them up later. */
+ uint32x4_t special = vorrq_u32 (vcgtq_u32 (iax, d->large_bound),
+ vcltq_u32 (iax, v_u32 (0x34000000)));
+ x = v_zerofy_f32 (x, is_boring);
+ if (__glibc_unlikely (v_any_u32 (special)))
+ x = v_zerofy_f32 (x, special);
+#else
+ uint32x4_t special = vcgtq_u32 (iax, d->large_bound);
+#endif
+
+ /* tanh(x) = (e^2x - 1) / (e^2x + 1). */
+ float32x4_t q = expm1f_inline (vmulq_n_f32 (x, 2), &d->expm1f_consts);
+ float32x4_t y = vdivq_f32 (q, vaddq_f32 (q, v_f32 (2.0)));
+ if (__glibc_unlikely (v_any_u32 (special)))
+ return special_case (vreinterpretq_f32_u32 (ix),
+ vbslq_f32 (is_boring, boring, y), special);
+ return vbslq_f32 (is_boring, boring, y);
+}
+libmvec_hidden_def (V_NAME_F1 (tanh))
+HALF_WIDTH_ALIAS_F1 (tanh)
diff --git a/sysdeps/aarch64/fpu/tanhf_sve.c b/sysdeps/aarch64/fpu/tanhf_sve.c
new file mode 100644
index 0000000000..0b94523cf5
--- /dev/null
+++ b/sysdeps/aarch64/fpu/tanhf_sve.c
@@ -0,0 +1,61 @@
+/* Single-precision vector (SVE) tanh function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_expm1f_inline.h"
+
+static const struct data
+{
+ struct sv_expm1f_data expm1f_consts;
+ uint32_t boring_bound, onef;
+} data = {
+ .expm1f_consts = SV_EXPM1F_DATA,
+ /* 0x1.205966p+3, above which tanhf rounds to 1 (or -1 for negative). */
+ .boring_bound = 0x41102cb3,
+ .onef = 0x3f800000,
+};
+
+static svfloat32_t NOINLINE
+special_case (svfloat32_t x, svfloat32_t y, svbool_t special)
+{
+ return sv_call_f32 (tanhf, x, y, special);
+}
+
+/* Approximation for single-precision SVE tanh(x), using a simplified
+ version of expm1f. The maximum error is 2.57 ULP:
+ _ZGVsMxv_tanhf (0x1.fc1832p-5) got 0x1.fb71a4p-5
+ want 0x1.fb71aap-5. */
+svfloat32_t SV_NAME_F1 (tanh) (svfloat32_t x, const svbool_t pg)
+{
+ const struct data *d = ptr_barrier (&data);
+
+ svfloat32_t ax = svabs_x (pg, x);
+ svuint32_t iax = svreinterpret_u32 (ax);
+ svuint32_t sign = sveor_x (pg, svreinterpret_u32 (x), iax);
+ svbool_t is_boring = svcmpgt (pg, iax, d->boring_bound);
+ svfloat32_t boring = svreinterpret_f32 (svorr_x (pg, sign, d->onef));
+
+ svbool_t special = svcmpgt (pg, iax, 0x7f800000);
+
+ /* tanh(x) = (e^2x - 1) / (e^2x + 1). */
+ svfloat32_t q = expm1f_inline (svmul_x (pg, x, 2.0), pg, &d->expm1f_consts);
+ svfloat32_t y = svdiv_x (pg, q, svadd_x (pg, q, 2.0));
+ if (__glibc_unlikely (svptest_any (pg, special)))
+ return special_case (x, svsel_f32 (is_boring, boring, y), special);
+ return svsel_f32 (is_boring, boring, y);
+}
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index 1a57b22c3a..7aeda880bd 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -44,3 +44,4 @@ VPCS_VECTOR_WRAPPER (log2_advsimd, _ZGVnN2v_log2)
VPCS_VECTOR_WRAPPER (sin_advsimd, _ZGVnN2v_sin)
VPCS_VECTOR_WRAPPER (sinh_advsimd, _ZGVnN2v_sinh)
VPCS_VECTOR_WRAPPER (tan_advsimd, _ZGVnN2v_tan)
+VPCS_VECTOR_WRAPPER (tanh_advsimd, _ZGVnN2v_tanh)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 0c9858f6b7..95f1ec5222 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -63,3 +63,4 @@ SVE_VECTOR_WRAPPER (log2_sve, _ZGVsMxv_log2)
SVE_VECTOR_WRAPPER (sin_sve, _ZGVsMxv_sin)
SVE_VECTOR_WRAPPER (sinh_sve, _ZGVsMxv_sinh)
SVE_VECTOR_WRAPPER (tan_sve, _ZGVsMxv_tan)
+SVE_VECTOR_WRAPPER (tanh_sve, _ZGVsMxv_tanh)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index 4758490c6f..bd6800e91c 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -44,3 +44,4 @@ VPCS_VECTOR_WRAPPER (log2f_advsimd, _ZGVnN4v_log2f)
VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf)
VPCS_VECTOR_WRAPPER (sinhf_advsimd, _ZGVnN4v_sinhf)
VPCS_VECTOR_WRAPPER (tanf_advsimd, _ZGVnN4v_tanf)
+VPCS_VECTOR_WRAPPER (tanhf_advsimd, _ZGVnN4v_tanhf)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index 7c04f07bbe..35ca305fdd 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -63,3 +63,4 @@ SVE_VECTOR_WRAPPER (log2f_sve, _ZGVsMxv_log2f)
SVE_VECTOR_WRAPPER (sinf_sve, _ZGVsMxv_sinf)
SVE_VECTOR_WRAPPER (sinhf_sve, _ZGVsMxv_sinhf)
SVE_VECTOR_WRAPPER (tanf_sve, _ZGVsMxv_tanf)
+SVE_VECTOR_WRAPPER (tanhf_sve, _ZGVsMxv_tanhf)
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index 004eb34694..c26d39e644 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -1496,11 +1496,19 @@ double: 2
float: 2
ldouble: 2
+Function: "tanh_advsimd":
+double: 2
+float: 2
+
Function: "tanh_downward":
double: 3
float: 3
ldouble: 4
+Function: "tanh_sve":
+double: 2
+float: 2
+
Function: "tanh_towardzero":
double: 2
float: 2
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index 1db5ba61d6..396082f6a7 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -85,12 +85,15 @@ GLIBC_2.40 _ZGVnN2v_erf F
GLIBC_2.40 _ZGVnN2v_erff F
GLIBC_2.40 _ZGVnN2v_sinh F
GLIBC_2.40 _ZGVnN2v_sinhf F
+GLIBC_2.40 _ZGVnN2v_tanh F
+GLIBC_2.40 _ZGVnN2v_tanhf F
GLIBC_2.40 _ZGVnN4v_acoshf F
GLIBC_2.40 _ZGVnN4v_asinhf F
GLIBC_2.40 _ZGVnN4v_atanhf F
GLIBC_2.40 _ZGVnN4v_coshf F
GLIBC_2.40 _ZGVnN4v_erff F
GLIBC_2.40 _ZGVnN4v_sinhf F
+GLIBC_2.40 _ZGVnN4v_tanhf F
GLIBC_2.40 _ZGVsMxv_acosh F
GLIBC_2.40 _ZGVsMxv_acoshf F
GLIBC_2.40 _ZGVsMxv_asinh F
@@ -103,3 +106,5 @@ GLIBC_2.40 _ZGVsMxv_erf F
GLIBC_2.40 _ZGVsMxv_erff F
GLIBC_2.40 _ZGVsMxv_sinh F
GLIBC_2.40 _ZGVsMxv_sinhf F
+GLIBC_2.40 _ZGVsMxv_tanh F
+GLIBC_2.40 _ZGVsMxv_tanhf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 8/8] aarch64/fpu: Add vector variants of erfc
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
` (5 preceding siblings ...)
2024-02-20 16:59 ` [PATCH 7/8] aarch64/fpu: Add vector variants of tanh Joe Ramsay
@ 2024-02-20 16:59 ` Joe Ramsay
2024-03-21 14:52 ` Szabolcs Nagy
2024-03-21 14:37 ` [PATCH 1/8] aarch64/fpu: Add vector variants of erf Szabolcs Nagy
7 siblings, 1 reply; 16+ messages in thread
From: Joe Ramsay @ 2024-02-20 16:59 UTC (permalink / raw)
To: libc-alpha; +Cc: Joe Ramsay
---
Thanks,
Joe
sysdeps/aarch64/fpu/Makefile | 5 +-
sysdeps/aarch64/fpu/Versions | 5 +
sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
sysdeps/aarch64/fpu/erfc_advsimd.c | 201 +
sysdeps/aarch64/fpu/erfc_data.c | 3519 +++++++++++++++++
sysdeps/aarch64/fpu/erfc_sve.c | 167 +
sysdeps/aarch64/fpu/erfcf_advsimd.c | 170 +
sysdeps/aarch64/fpu/erfcf_data.c | 676 ++++
sysdeps/aarch64/fpu/erfcf_sve.c | 113 +
.../fpu/test-double-advsimd-wrappers.c | 1 +
.../aarch64/fpu/test-double-sve-wrappers.c | 1 +
.../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
sysdeps/aarch64/fpu/vecmath_config.h | 16 +
sysdeps/aarch64/libm-test-ulps | 8 +
.../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
17 files changed, 4897 insertions(+), 1 deletion(-)
create mode 100644 sysdeps/aarch64/fpu/erfc_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/erfc_data.c
create mode 100644 sysdeps/aarch64/fpu/erfc_sve.c
create mode 100644 sysdeps/aarch64/fpu/erfcf_advsimd.c
create mode 100644 sysdeps/aarch64/fpu/erfcf_data.c
create mode 100644 sysdeps/aarch64/fpu/erfcf_sve.c
diff --git a/sysdeps/aarch64/fpu/Makefile b/sysdeps/aarch64/fpu/Makefile
index e5f418ae42..e8af35099d 100644
--- a/sysdeps/aarch64/fpu/Makefile
+++ b/sysdeps/aarch64/fpu/Makefile
@@ -8,6 +8,7 @@ libmvec-supported-funcs = acos \
cos \
cosh \
erf \
+ erfc \
exp \
exp10 \
exp2 \
@@ -39,7 +40,9 @@ libmvec-support = $(addsuffix f_advsimd,$(float-advsimd-funcs)) \
erff_data \
sv_erf_data \
sv_erff_data \
- v_exp_tail_data
+ v_exp_tail_data \
+ erfc_data \
+ erfcf_data
endif
sve-cflags = -march=armv8-a+sve
diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
index 4dbf3d3244..3cb1b82bd2 100644
--- a/sysdeps/aarch64/fpu/Versions
+++ b/sysdeps/aarch64/fpu/Versions
@@ -104,6 +104,11 @@ libmvec {
_ZGVnN4v_erff;
_ZGVsMxv_erf;
_ZGVsMxv_erff;
+ _ZGVnN2v_erfc;
+ _ZGVnN2v_erfcf;
+ _ZGVnN4v_erfcf;
+ _ZGVsMxv_erfc;
+ _ZGVsMxv_erfcf;
_ZGVnN2v_sinh;
_ZGVnN2v_sinhf;
_ZGVnN4v_sinhf;
diff --git a/sysdeps/aarch64/fpu/advsimd_f32_protos.h b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
index 4ff191c324..383c436972 100644
--- a/sysdeps/aarch64/fpu/advsimd_f32_protos.h
+++ b/sysdeps/aarch64/fpu/advsimd_f32_protos.h
@@ -26,6 +26,7 @@ libmvec_hidden_proto (V_NAME_F1(atanh));
libmvec_hidden_proto (V_NAME_F1(cos));
libmvec_hidden_proto (V_NAME_F1(cosh));
libmvec_hidden_proto (V_NAME_F1(erf));
+libmvec_hidden_proto (V_NAME_F1(erfc));
libmvec_hidden_proto (V_NAME_F1(exp10));
libmvec_hidden_proto (V_NAME_F1(exp2));
libmvec_hidden_proto (V_NAME_F1(exp));
diff --git a/sysdeps/aarch64/fpu/bits/math-vector.h b/sysdeps/aarch64/fpu/bits/math-vector.h
index 585e022082..e29b2d1c09 100644
--- a/sysdeps/aarch64/fpu/bits/math-vector.h
+++ b/sysdeps/aarch64/fpu/bits/math-vector.h
@@ -69,6 +69,10 @@
# define __DECL_SIMD_erf __DECL_SIMD_aarch64
# undef __DECL_SIMD_erff
# define __DECL_SIMD_erff __DECL_SIMD_aarch64
+# undef __DECL_SIMD_erfc
+# define __DECL_SIMD_erfc __DECL_SIMD_aarch64
+# undef __DECL_SIMD_erfcf
+# define __DECL_SIMD_erfcf __DECL_SIMD_aarch64
# undef __DECL_SIMD_exp
# define __DECL_SIMD_exp __DECL_SIMD_aarch64
# undef __DECL_SIMD_expf
@@ -153,6 +157,7 @@ __vpcs __f32x4_t _ZGVnN4v_atanhf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_cosf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_coshf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_erff (__f32x4_t);
+__vpcs __f32x4_t _ZGVnN4v_erfcf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_expf (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_exp10f (__f32x4_t);
__vpcs __f32x4_t _ZGVnN4v_exp2f (__f32x4_t);
@@ -176,6 +181,7 @@ __vpcs __f64x2_t _ZGVnN2v_atanh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cos (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_cosh (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_erf (__f64x2_t);
+__vpcs __f64x2_t _ZGVnN2v_erfc (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp10 (__f64x2_t);
__vpcs __f64x2_t _ZGVnN2v_exp2 (__f64x2_t);
@@ -204,6 +210,7 @@ __sv_f32_t _ZGVsMxv_atanhf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_cosf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_coshf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_erff (__sv_f32_t, __sv_bool_t);
+__sv_f32_t _ZGVsMxv_erfcf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_expf (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_exp10f (__sv_f32_t, __sv_bool_t);
__sv_f32_t _ZGVsMxv_exp2f (__sv_f32_t, __sv_bool_t);
@@ -227,6 +234,7 @@ __sv_f64_t _ZGVsMxv_atanh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cos (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_cosh (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_erf (__sv_f64_t, __sv_bool_t);
+__sv_f64_t _ZGVsMxv_erfc (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp10 (__sv_f64_t, __sv_bool_t);
__sv_f64_t _ZGVsMxv_exp2 (__sv_f64_t, __sv_bool_t);
diff --git a/sysdeps/aarch64/fpu/erfc_advsimd.c b/sysdeps/aarch64/fpu/erfc_advsimd.c
new file mode 100644
index 0000000000..548f21a3d6
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfc_advsimd.c
@@ -0,0 +1,201 @@
+/* Double-precision vector (Advanced SIMD) erfc function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+#include "vecmath_config.h"
+
+static const struct data
+{
+ uint64x2_t offset, table_scale;
+ float64x2_t max, shift;
+ float64x2_t p20, p40, p41, p42;
+ float64x2_t p51, p52;
+ float64x2_t qr5, qr6, qr7, qr8, qr9;
+#if WANT_SIMD_EXCEPT
+ float64x2_t uflow_bound;
+#endif
+} data = {
+ /* Set an offset so the range of the index used for lookup is 3487, and it
+ can be clamped using a saturated add on an offset index.
+ Index offset is 0xffffffffffffffff - asuint64(shift) - 3487. */
+ .offset = V2 (0xbd3ffffffffff260),
+ .table_scale = V2 (0x37f0000000000000 << 1), /* asuint64 (2^-128) << 1. */
+ .max = V2 (0x1.b3ep+4), /* 3487/128. */
+ .shift = V2 (0x1p45),
+ .p20 = V2 (0x1.5555555555555p-2), /* 1/3, used to compute 2/3 and 1/6. */
+ .p40 = V2 (-0x1.999999999999ap-4), /* 1/10. */
+ .p41 = V2 (-0x1.999999999999ap-2), /* 2/5. */
+ .p42 = V2 (0x1.1111111111111p-3), /* 2/15. */
+ .p51 = V2 (-0x1.c71c71c71c71cp-3), /* 2/9. */
+ .p52 = V2 (0x1.6c16c16c16c17p-5), /* 2/45. */
+ /* Qi = (i+1) / i, Ri = -2 * i / ((i+1)*(i+2)), for i = 5, ..., 9. */
+ .qr5 = { 0x1.3333333333333p0, -0x1.e79e79e79e79ep-3 },
+ .qr6 = { 0x1.2aaaaaaaaaaabp0, -0x1.b6db6db6db6dbp-3 },
+ .qr7 = { 0x1.2492492492492p0, -0x1.8e38e38e38e39p-3 },
+ .qr8 = { 0x1.2p0, -0x1.6c16c16c16c17p-3 },
+ .qr9 = { 0x1.1c71c71c71c72p0, -0x1.4f2094f2094f2p-3 },
+#if WANT_SIMD_EXCEPT
+ .uflow_bound = V2 (0x1.a8b12fc6e4892p+4),
+#endif
+};
+
+#define TinyBound 0x4000000000000000 /* 0x1p-511 << 1. */
+#define Off 0xfffffffffffff260 /* 0xffffffffffffffff - 3487. */
+
+struct entry
+{
+ float64x2_t erfc;
+ float64x2_t scale;
+};
+
+static inline struct entry
+lookup (uint64x2_t i)
+{
+ struct entry e;
+ float64x2_t e1 = vld1q_f64 ((float64_t *) (__erfc_data.tab - Off + i[0])),
+ e2 = vld1q_f64 ((float64_t *) (__erfc_data.tab - Off + i[1]));
+ e.erfc = vuzp1q_f64 (e1, e2);
+ e.scale = vuzp2q_f64 (e1, e2);
+ return e;
+}
+
+#if WANT_SIMD_EXCEPT
+static float64x2_t VPCS_ATTR NOINLINE
+special_case (float64x2_t x, float64x2_t y, uint64x2_t cmp)
+{
+ return v_call_f64 (erfc, x, y, cmp);
+}
+#endif
+
+/* Optimized double-precision vector erfc(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erfc(x) ~ erfc(r) - scale * d * poly(r, d), with
+
+ poly(r, d) = 1 - r d + (2/3 r^2 - 1/3) d^2 - r (1/3 r^2 - 1/2) d^3
+ + (2/15 r^4 - 2/5 r^2 + 1/10) d^4
+ - r * (2/45 r^4 - 2/9 r^2 + 1/6) d^5
+ + p6(r) d^6 + ... + p10(r) d^10
+
+ Polynomials p6(r) to p10(r) are computed using recurrence relation
+
+ 2(i+1)p_i + 2r(i+2)p_{i+1} + (i+2)(i+3)p_{i+2} = 0,
+ with p0 = 1, and p1(r) = -r.
+
+ Values of erfc(r) and scale are read from lookup tables. Stored values
+ are scaled to avoid hitting the subnormal range.
+
+ Note that for x < 0, erfc(x) = 2.0 - erfc(-x).
+
+ Maximum measured error: 1.71 ULP
+ V_NAME_D1 (erfc)(0x1.46cfe976733p+4) got 0x1.e15fcbea3e7afp-608
+ want 0x1.e15fcbea3e7adp-608. */
+VPCS_ATTR
+float64x2_t V_NAME_D1 (erfc) (float64x2_t x)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+#if WANT_SIMD_EXCEPT
+ /* |x| < 2^-511. Avoid fabs by left-shifting by 1. */
+ uint64x2_t ix = vreinterpretq_u64_f64 (x);
+ uint64x2_t cmp = vcltq_u64 (vaddq_u64 (ix, ix), v_u64 (TinyBound));
+ /* x >= ~26.54 (into subnormal case and uflow case). Comparison is done in
+ integer domain to avoid raising exceptions in presence of nans. */
+ uint64x2_t uflow = vcgeq_s64 (vreinterpretq_s64_f64 (x),
+ vreinterpretq_s64_f64 (dat->uflow_bound));
+ cmp = vorrq_u64 (cmp, uflow);
+ float64x2_t xm = x;
+ /* If any lanes are special, mask them with 0 and retain a copy of x to allow
+ special case handler to fix special lanes later. This is only necessary if
+ fenv exceptions are to be triggered correctly. */
+ if (__glibc_unlikely (v_any_u64 (cmp)))
+ x = v_zerofy_f64 (x, cmp);
+#endif
+
+ float64x2_t a = vabsq_f64 (x);
+ a = vminq_f64 (a, dat->max);
+
+ /* Lookup erfc(r) and scale(r) in tables, e.g. set erfc(r) to 0 and scale to
+ 2/sqrt(pi), when x reduced to r = 0. */
+ float64x2_t shift = dat->shift;
+ float64x2_t z = vaddq_f64 (a, shift);
+
+ /* Clamp index to a range of 3487. A naive approach would use a subtract and
+ min. Instead we offset the table address and the index, then use a
+ saturating add. */
+ uint64x2_t i = vqaddq_u64 (vreinterpretq_u64_f64 (z), dat->offset);
+
+ struct entry e = lookup (i);
+
+ /* erfc(x) ~ erfc(r) - scale * d * poly(r, d). */
+ float64x2_t r = vsubq_f64 (z, shift);
+ float64x2_t d = vsubq_f64 (a, r);
+ float64x2_t d2 = vmulq_f64 (d, d);
+ float64x2_t r2 = vmulq_f64 (r, r);
+
+ float64x2_t p1 = r;
+ float64x2_t p2 = vfmsq_f64 (dat->p20, r2, vaddq_f64 (dat->p20, dat->p20));
+ float64x2_t p3 = vmulq_f64 (r, vfmaq_f64 (v_f64 (-0.5), r2, dat->p20));
+ float64x2_t p4 = vfmaq_f64 (dat->p41, r2, dat->p42);
+ p4 = vfmsq_f64 (dat->p40, r2, p4);
+ float64x2_t p5 = vfmaq_f64 (dat->p51, r2, dat->p52);
+ p5 = vmulq_f64 (r, vfmaq_f64 (vmulq_f64 (v_f64 (0.5), dat->p20), r2, p5));
+ /* Compute p_i using recurrence relation:
+ p_{i+2} = (p_i + r * Q_{i+1} * p_{i+1}) * R_{i+1}. */
+ float64x2_t p6 = vfmaq_f64 (p4, p5, vmulq_laneq_f64 (r, dat->qr5, 0));
+ p6 = vmulq_laneq_f64 (p6, dat->qr5, 1);
+ float64x2_t p7 = vfmaq_f64 (p5, p6, vmulq_laneq_f64 (r, dat->qr6, 0));
+ p7 = vmulq_laneq_f64 (p7, dat->qr6, 1);
+ float64x2_t p8 = vfmaq_f64 (p6, p7, vmulq_laneq_f64 (r, dat->qr7, 0));
+ p8 = vmulq_laneq_f64 (p8, dat->qr7, 1);
+ float64x2_t p9 = vfmaq_f64 (p7, p8, vmulq_laneq_f64 (r, dat->qr8, 0));
+ p9 = vmulq_laneq_f64 (p9, dat->qr8, 1);
+ float64x2_t p10 = vfmaq_f64 (p8, p9, vmulq_laneq_f64 (r, dat->qr9, 0));
+ p10 = vmulq_laneq_f64 (p10, dat->qr9, 1);
+ /* Compute polynomial in d using pairwise Horner scheme. */
+ float64x2_t p90 = vfmaq_f64 (p9, d, p10);
+ float64x2_t p78 = vfmaq_f64 (p7, d, p8);
+ float64x2_t p56 = vfmaq_f64 (p5, d, p6);
+ float64x2_t p34 = vfmaq_f64 (p3, d, p4);
+ float64x2_t p12 = vfmaq_f64 (p1, d, p2);
+ float64x2_t y = vfmaq_f64 (p78, d2, p90);
+ y = vfmaq_f64 (p56, d2, y);
+ y = vfmaq_f64 (p34, d2, y);
+ y = vfmaq_f64 (p12, d2, y);
+
+ y = vfmsq_f64 (e.erfc, e.scale, vfmsq_f64 (d, d2, y));
+
+ /* Offset equals 2.0 if sign, else 0.0. */
+ uint64x2_t sign = vshrq_n_u64 (vreinterpretq_u64_f64 (x), 63);
+ float64x2_t off = vreinterpretq_f64_u64 (vshlq_n_u64 (sign, 62));
+ /* Copy sign and scale back in a single fma. Since the bit patterns do not
+ overlap, then logical or and addition are equivalent here. */
+ float64x2_t fac = vreinterpretq_f64_u64 (
+ vsraq_n_u64 (vshlq_n_u64 (sign, 63), dat->table_scale, 1));
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u64 (cmp)))
+ return special_case (xm, vfmaq_f64 (off, fac, y), cmp);
+#endif
+
+ return vfmaq_f64 (off, fac, y);
+}
diff --git a/sysdeps/aarch64/fpu/erfc_data.c b/sysdeps/aarch64/fpu/erfc_data.c
new file mode 100644
index 0000000000..76a94e4681
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfc_data.c
@@ -0,0 +1,3519 @@
+/* Table for Advanced SIMD erfc
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in erfc.
+ For each possible rounded input r (multiples of 1/128), between
+ r = 0.0 and r = ~27.0 (3488 values):
+ - the first entry __erfc_data.tab.erfc contains the values of erfc(r),
+ - the second entry __erfc_data.tab.scale contains the values of
+ 2/sqrt(pi)*exp(-r^2). Both values may go into subnormal range, therefore
+ they are scaled by a large enough value 2^128 (fits in 8bit). */
+const struct erfc_data __erfc_data = {
+ .tab = { { 0x1p128, 0x1.20dd750429b6dp128 },
+ { 0x1.fb7c9030853b3p127, 0x1.20d8f1975c85dp128 },
+ { 0x1.f6f9447be0743p127, 0x1.20cb67bd452c7p128 },
+ { 0x1.f27640f9853d9p127, 0x1.20b4d8bac36c1p128 },
+ { 0x1.edf3a9ba22dadp127, 0x1.209546ad13ccfp128 },
+ { 0x1.e971a2c4436aep127, 0x1.206cb4897b148p128 },
+ { 0x1.e4f05010eca8cp127, 0x1.203b261cd0053p128 },
+ { 0x1.e06fd58842c7ep127, 0x1.2000a00ae3804p128 },
+ { 0x1.dbf056fe2df35p127, 0x1.1fbd27cdc72d3p128 },
+ { 0x1.d771f82f02f4ep127, 0x1.1f70c3b4f2cc8p128 },
+ { 0x1.d2f4dcbc2f894p127, 0x1.1f1b7ae44867fp128 },
+ { 0x1.ce792828eae5cp127, 0x1.1ebd5552f795bp128 },
+ { 0x1.c9fefdd6eaf19p127, 0x1.1e565bca400d4p128 },
+ { 0x1.c58681031eb6ap127, 0x1.1de697e413d29p128 },
+ { 0x1.c10fd4c26e896p127, 0x1.1d6e14099944ap128 },
+ { 0x1.bc9b1bfe82687p127, 0x1.1cecdb718d61cp128 },
+ { 0x1.b82879728f11ep127, 0x1.1c62fa1e869b6p128 },
+ { 0x1.b3b80fa82a4bbp127, 0x1.1bd07cdd189acp128 },
+ { 0x1.af4a00f426daap127, 0x1.1b357141d95d5p128 },
+ { 0x1.aade6f7378a0ep127, 0x1.1a91e5a748165p128 },
+ { 0x1.a6757d08215d8p127, 0x1.19e5e92b964abp128 },
+ { 0x1.a20f4b5626818p127, 0x1.19318bae53a04p128 },
+ { 0x1.9dabfbc090901p127, 0x1.1874ddcdfce24p128 },
+ { 0x1.994baf66747adp127, 0x1.17aff0e56ec1p128 },
+ { 0x1.94ee8720076b6p127, 0x1.16e2d7093cd8cp128 },
+ { 0x1.9094a37bbd66ep127, 0x1.160da304ed92fp128 },
+ { 0x1.8c3e24bb73372p127, 0x1.153068581b781p128 },
+ { 0x1.87eb2ad1a4032p127, 0x1.144b3b337c90cp128 },
+ { 0x1.839bd55eaafc8p127, 0x1.135e3075d076bp128 },
+ { 0x1.7f5043ae11862p127, 0x1.12695da8b5bdep128 },
+ { 0x1.7b0894b3ea35cp127, 0x1.116cd8fd67618p128 },
+ { 0x1.76c4e70a390e7p127, 0x1.1068b94962e5ep128 },
+ { 0x1.728558ee694fcp127, 0x1.0f5d1602f7e41p128 },
+ { 0x1.6e4a083ed132fp127, 0x1.0e4a073dc1b91p128 },
+ { 0x1.6a13127843ec1p127, 0x1.0d2fa5a70c168p128 },
+ { 0x1.65e094b3b2413p127, 0x1.0c0e0a8223359p128 },
+ { 0x1.61b2aba3da093p127, 0x1.0ae54fa490723p128 },
+ { 0x1.5d89739304dcfp127, 0x1.09b58f724416bp128 },
+ { 0x1.59650860d6469p127, 0x1.087ee4d9ad247p128 },
+ { 0x1.5545858029b39p127, 0x1.07416b4fbfe7cp128 },
+ { 0x1.512b05f5006e1p127, 0x1.05fd3ecbec298p128 },
+ { 0x1.4d15a4527fdc7p127, 0x1.04b27bc403d3p128 },
+ { 0x1.49057ab900447p127, 0x1.03613f2812dafp128 },
+ { 0x1.44faa2d42c4ap127, 0x1.0209a65e29545p128 },
+ { 0x1.40f535d93160ep127, 0x1.00abcf3e187a9p128 },
+ { 0x1.3cf54c850162p127, 0x1.fe8fb01a47307p127 },
+ { 0x1.38faff1aa574ap127, 0x1.fbbbbef34b4b2p127 },
+ { 0x1.35066561a275dp127, 0x1.f8dc092d58ff8p127 },
+ { 0x1.311796a46f064p127, 0x1.f5f0cdaf15313p127 },
+ { 0x1.2d2ea9aefb636p127, 0x1.f2fa4c16c0019p127 },
+ { 0x1.294bb4cd4b2bdp127, 0x1.eff8c4b1375dbp127 },
+ { 0x1.256ecdca212ccp127, 0x1.ecec7870ebca8p127 },
+ { 0x1.219809edbd524p127, 0x1.e9d5a8e4c934ep127 },
+ { 0x1.1dc77dfcacd02p127, 0x1.e6b4982f158b9p127 },
+ { 0x1.19fd3e36ac96ap127, 0x1.e38988fc46e72p127 },
+ { 0x1.16395e559e218p127, 0x1.e054be79d3042p127 },
+ { 0x1.127bf18c8eadcp127, 0x1.dd167c4cf9d2ap127 },
+ { 0x1.0ec50a86d0dd4p127, 0x1.d9cf06898cdafp127 },
+ { 0x1.0b14bb6728cd8p127, 0x1.d67ea1a8b5368p127 },
+ { 0x1.076b15c70aa28p127, 0x1.d325927fb9d89p127 },
+ { 0x1.03c82ab5eb831p127, 0x1.cfc41e36c7df9p127 },
+ { 0x1.002c0ab8a5018p127, 0x1.cc5a8a3fbea4p127 },
+ { 0x1.f92d8b91d5cc7p126, 0x1.c8e91c4d01368p127 },
+ { 0x1.f210d6a9a6a31p126, 0x1.c5701a484ef9dp127 },
+ { 0x1.eb02147ce245cp126, 0x1.c1efca49a5011p127 },
+ { 0x1.e40161b701275p126, 0x1.be68728e29d5ep127 },
+ { 0x1.dd0ed9ea4bdd6p126, 0x1.bada596f25436p127 },
+ { 0x1.d62a978f7c957p126, 0x1.b745c55905bf8p127 },
+ { 0x1.cf54b4058455fp126, 0x1.b3aafcc27502ep127 },
+ { 0x1.c88d479173ccep126, 0x1.b00a46237d5bep127 },
+ { 0x1.c1d4695e87644p126, 0x1.ac63e7ecc1411p127 },
+ { 0x1.bb2a2f7e5652p126, 0x1.a8b8287ec6a09p127 },
+ { 0x1.b48eaee924501p126, 0x1.a5074e215762p127 },
+ { 0x1.ae01fb7e55a66p126, 0x1.a1519efaf889ep127 },
+ { 0x1.a78428050527ep126, 0x1.9d97610879642p127 },
+ { 0x1.a115462cbbc17p126, 0x1.99d8da149c13fp127 },
+ { 0x1.9ab5668e4930ap126, 0x1.96164fafd8de3p127 },
+ { 0x1.946498acbd766p126, 0x1.925007283d7aap127 },
+ { 0x1.8e22eaf68291ep126, 0x1.8e86458169af8p127 },
+ { 0x1.87f06ac6960c4p126, 0x1.8ab94f6caa71dp127 },
+ { 0x1.81cd2465e1d96p126, 0x1.86e9694134b9ep127 },
+ { 0x1.7bb9230cb40b4p126, 0x1.8316d6f48133dp127 },
+ { 0x1.75b470e454d35p126, 0x1.7f41dc12c9e89p127 },
+ { 0x1.6fbf1708ba47cp126, 0x1.7b6abbb7aaf19p127 },
+ { 0x1.69d91d8a595dap126, 0x1.7791b886e7403p127 },
+ { 0x1.64028b7013867p126, 0x1.73b714a552763p127 },
+ { 0x1.5e3b66b9405a9p126, 0x1.6fdb11b1e0c34p127 },
+ { 0x1.5883b45fd2b63p126, 0x1.6bfdf0beddaf5p127 },
+ { 0x1.52db785a98acap126, 0x1.681ff24b4ab04p127 },
+ { 0x1.4d42b59f95afap126, 0x1.6441563c665d4p127 },
+ { 0x1.47b96e267647ap126, 0x1.60625bd75d07bp127 },
+ { 0x1.423fa2eb1cb59p126, 0x1.5c8341bb23767p127 },
+ { 0x1.3cd553f045d45p126, 0x1.58a445da7c74cp127 },
+ { 0x1.377a8042458d1p126, 0x1.54c5a57629dbp127 },
+ { 0x1.322f25f9da2fdp126, 0x1.50e79d1749ac9p127 },
+ { 0x1.2cf3423f15fdfp126, 0x1.4d0a6889dfd9fp127 },
+ { 0x1.27c6d14c5e341p126, 0x1.492e42d78d2c5p127 },
+ { 0x1.22a9ce717edcbp126, 0x1.4553664273d24p127 },
+ { 0x1.1d9c3416d2b4bp126, 0x1.417a0c4049fdp127 },
+ { 0x1.189dfbc07e69p126, 0x1.3da26d759aef5p127 },
+ { 0x1.13af1e11be721p126, 0x1.39ccc1b136d5ap127 },
+ { 0x1.0ecf92d046d22p126, 0x1.35f93fe7d1b3dp127 },
+ { 0x1.09ff50e7b3f93p126, 0x1.32281e2fd1a92p127 },
+ { 0x1.053e4e6d0c10bp126, 0x1.2e5991bd4cbfcp127 },
+ { 0x1.008c80a24ff1p126, 0x1.2a8dcede3673bp127 },
+ { 0x1.f7d3b7f436013p125, 0x1.26c508f6bd0ffp127 },
+ { 0x1.eeaca836a27ccp125, 0x1.22ff727dd6f7bp127 },
+ { 0x1.e5a3b7c9b56dap125, 0x1.1f3d3cf9ffe5ap127 },
+ { 0x1.dcb8cae2d747fp125, 0x1.1b7e98fe26217p127 },
+ { 0x1.d3ebc436b0f26p125, 0x1.17c3b626c7a12p127 },
+ { 0x1.cb3c8500ea349p125, 0x1.140cc3173f007p127 },
+ { 0x1.c2aaed0bfcfeep125, 0x1.1059ed7740313p127 },
+ { 0x1.ba36dab91c0e9p125, 0x1.0cab61f084b93p127 },
+ { 0x1.b1e02b082b72p125, 0x1.09014c2ca74dap127 },
+ { 0x1.a9a6b99fc973bp125, 0x1.055bd6d32e8d7p127 },
+ { 0x1.a18a60d56673ep125, 0x1.01bb2b87c6968p127 },
+ { 0x1.998af9b56a3aep125, 0x1.fc3ee5d1524bp126 },
+ { 0x1.91a85c0b65519p125, 0x1.f511a91a67d2ap126 },
+ { 0x1.89e25e6a4cef9p125, 0x1.edeeee0959518p126 },
+ { 0x1.8238d634c0127p125, 0x1.e6d6ffaa65a25p126 },
+ { 0x1.7aab97a554544p125, 0x1.dfca26f5bbf88p126 },
+ { 0x1.733a75d6e91b8p125, 0x1.d8c8aace11e63p126 },
+ { 0x1.6be542ccffc2fp125, 0x1.d1d2cfff91594p126 },
+ { 0x1.64abcf7c175b4p125, 0x1.cae8d93f1d7b7p126 },
+ { 0x1.5d8debd20aacep125, 0x1.c40b0729ed548p126 },
+ { 0x1.568b66be6f268p125, 0x1.bd3998457afdbp126 },
+ { 0x1.4fa40e3af3674p125, 0x1.b674c8ffc6283p126 },
+ { 0x1.48d7af53bc19fp125, 0x1.afbcd3afe8ab6p126 },
+ { 0x1.4226162fbddd5p125, 0x1.a911f096fbc26p126 },
+ { 0x1.3b8f0e1912f7p125, 0x1.a27455e14c93cp126 },
+ { 0x1.351261854b991p125, 0x1.9be437a7de946p126 },
+ { 0x1.2eafda1db784ap125, 0x1.9561c7f23a47bp126 },
+ { 0x1.286740c7a7dabp125, 0x1.8eed36b886d93p126 },
+ { 0x1.22385daca7f47p125, 0x1.8886b1e5ecfd1p126 },
+ { 0x1.1c22f842ac1f2p125, 0x1.822e655b417e7p126 },
+ { 0x1.1626d7543522p125, 0x1.7be47af1f5d89p126 },
+ { 0x1.1043c1086777dp125, 0x1.75a91a7f4d2edp126 },
+ { 0x1.0a797aeb152f2p125, 0x1.6f7c69d7d3ef8p126 },
+ { 0x1.04c7c9f4b969p125, 0x1.695e8cd31867ep126 },
+ { 0x1.fe5ce524c8ee5p124, 0x1.634fa54fa285fp126 },
+ { 0x1.f35a715b2f3e1p124, 0x1.5d4fd33729015p126 },
+ { 0x1.e887bf681f218p124, 0x1.575f3483021c3p126 },
+ { 0x1.dde4553ef94dep124, 0x1.517de540ce2a3p126 },
+ { 0x1.d36fb7fa50177p124, 0x1.4babff975a04cp126 },
+ { 0x1.c9296beb09cf1p124, 0x1.45e99bcbb7915p126 },
+ { 0x1.bf10f4a759889p124, 0x1.4036d0468a7a2p126 },
+ { 0x1.b525d5198cb1cp124, 0x1.3a93b1998736cp126 },
+ { 0x1.ab678f8eabedbp124, 0x1.35005285227f1p126 },
+ { 0x1.a1d5a5c4edb96p124, 0x1.2f7cc3fe6f423p126 },
+ { 0x1.986f98f9f96c8p124, 0x1.2a09153529381p126 },
+ { 0x1.8f34e9f8f93a6p124, 0x1.24a55399ea239p126 },
+ { 0x1.8625192879e39p124, 0x1.1f518ae487dc8p126 },
+ { 0x1.7d3fa69816db5p124, 0x1.1a0dc51a9934dp126 },
+ { 0x1.7484120df1b01p124, 0x1.14da0a961fd14p126 },
+ { 0x1.6bf1db13f3983p124, 0x1.0fb6620c550afp126 },
+ { 0x1.63888104d811ap124, 0x1.0aa2d09497f2bp126 },
+ { 0x1.5b478318ff939p124, 0x1.059f59af7a906p126 },
+ { 0x1.532e6073095f2p124, 0x1.00abff4dec7a3p126 },
+ { 0x1.4b3c982c338c7p124, 0x1.f79183b101c5bp125 },
+ { 0x1.4371a960807f8p124, 0x1.edeb406d9c825p125 },
+ { 0x1.3bcd133aa0ffcp124, 0x1.e4652fadcb6b2p125 },
+ { 0x1.344e54ffa23b9p124, 0x1.daff4969c0b04p125 },
+ { 0x1.2cf4ee1a5f0fcp124, 0x1.d1b982c50137p125 },
+ { 0x1.25c05e26b3f99p124, 0x1.c893ce1dcbef7p125 },
+ { 0x1.1eb024fc75285p124, 0x1.bf8e1b1ca2279p125 },
+ { 0x1.17c3c2ba26319p124, 0x1.b6a856c3ed54fp125 },
+ { 0x1.10fab7cf72f94p124, 0x1.ade26b7fbed95p125 },
+ { 0x1.0a548507696cp124, 0x1.a53c4135a6526p125 },
+ { 0x1.03d0ab9273b94p124, 0x1.9cb5bd549b111p125 },
+ { 0x1.fadd5a20258d3p123, 0x1.944ec2e4f563p125 },
+ { 0x1.ee5c1730b147cp123, 0x1.8c07329874652p125 },
+ { 0x1.e21c938a45a83p123, 0x1.83deeada4d25ap125 },
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+ { 0x1.d246bba093dddp-915, 0x1.86d89be61c44fp-909 },
+ { 0x1.329e3d8fc35e5p-915, 0x1.011744722e8f8p-909 },
+ { 0x1.93354aecb0f91p-916, 0x1.522d67c700dd9p-910 },
+ { 0x1.09149eae599f4p-916, 0x1.bcc8c2b79e5e6p-911 },
+ { 0x1.5c8020a89d6a7p-917, 0x1.247692feaf7c7p-911 },
+ { 0x1.ca1dd59404578p-918, 0x1.8090b25f1fb1cp-912 },
+ { 0x1.2d1194826d1d9p-918, 0x1.f99c33fa36826p-913 },
+ { 0x1.8bab4cd7bc185p-919, 0x1.4c563ff8738edp-913 },
+ { 0x1.03f72f0fa181cp-919, 0x1.b4d5ff233ee8bp-914 },
+ { 0x1.559144638d7d2p-920, 0x1.1f0fc4fe41aefp-914 },
+ { 0x1.c0baa10766979p-921, 0x1.793b75fbd2367p-915 },
+ { 0x1.26b830bbc4f33p-921, 0x1.efaa9eeaa4992p-916 },
+ { 0x1.8316ba6f8ef74p-922, 0x1.459a26ac43fcfp-916 },
+ { 0x1.fc588d5eeb3p-923, 0x1.abb8ece685efep-917 },
+ { 0x1.4dc0c0d42f863p-923, 0x1.18e6b704952c1p-917 },
+ { 0x1.b6320aea7077ap-924, 0x1.70e95e366ca95p-918 },
+ { 0x1.1fa02ebad6485p-924, 0x1.e4700e7fab75ep-919 },
+ { 0x1.798a96e59845bp-925, 0x1.3e0826243926dp-919 },
+ { 0x1.ef81624855ca5p-926, 0x1.a185d71d9ae78p-920 },
+ { 0x1.451fcaaed5e7p-926, 0x1.1209163a43d8ap-920 },
+ { 0x1.aa9b30dd7b333p-927, 0x1.67acd56555624p-921 },
+ { 0x1.17d9121b4ff43p-927, 0x1.d805487b20ec2p-922 },
+ { 0x1.6f1bb0c9eff18p-928, 0x1.35b0e3e76f72ap-922 },
+ { 0x1.e184bec96bcc5p-929, 0x1.965317fc3f8ebp-923 },
+ { 0x1.3bc10ccdff1d7p-929, 0x1.0a85e11600392p-923 },
+ { 0x1.9e0f0cdf83a76p-930, 0x1.5d99f4f4fa7a2p-924 },
+ { 0x1.0f738d3253e75p-930, 0x1.ca8538b911cc2p-925 },
+ { 0x1.63e056b37b486p-931, 0x1.2ca663e8f6c6ep-925 },
+ { 0x1.d2806afda0512p-932, 0x1.8a38c763ae5p-926 },
+ { 0x1.31b865207923bp-932, 0x1.026d30f31261ep-926 },
+ { 0x1.90a81bef15367p-933, 0x1.52c63cbe5201dp-927 },
+ { 0x1.068145905baddp-933, 0x1.bc0c903e2dd51p-928 },
+ { 0x1.57f0081c7461bp-934, 0x1.22fbc7eb40c8ep-928 },
+ { 0x1.c293abfeb81c1p-935, 0x1.7d5064d5d2e6ap-929 },
+ { 0x1.271a9ed146425p-935, 0x1.f3a001a1da12ap-930 },
+ { 0x1.8282015bfd093p-936, 0x1.474846e880b8p-930 },
+ { 0x1.fa292d1f4b615p-937, 0x1.acb96019278e3p-931 },
+ { 0x1.4b6323fa7fafcp-937, 0x1.18c50c637e437p-931 },
+ { 0x1.b1ded81f6cf48p-938, 0x1.6fb47e7243b1p-932 },
+ { 0x1.1bfd2aff12d23p-938, 0x1.e17fe4af1cdcdp-933 },
+ { 0x1.73b9288cf980bp-939, 0x1.3b3779cd081bcp-933 },
+ { 0x1.e680a6315c8f9p-940, 0x1.9caab20737c4bp-934 },
+ { 0x1.3e52969a46a03p-940, 0x1.0e16c42489121p-934 },
+ { 0x1.a082ea93d471fp-941, 0x1.618056ad2fa0dp-935 },
+ { 0x1.1075d9566cab2p-941, 0x1.ce9e247afa7efp-936 },
+ { 0x1.646a66f6fb197p-942, 0x1.2eabb9557e4c3p-936 },
+ { 0x1.d22f0f82317a8p-943, 0x1.8c0020c90fd02p-937 },
+ { 0x1.30d7883df3e07p-943, 0x1.0305d4157bdecp-937 },
+ { 0x1.8ea1187daf8b3p-944, 0x1.52cf8a69cbdeep-938 },
+ { 0x1.049a91d747c02p-944, 0x1.bb1f3a4ce848cp-939 },
+ { 0x1.54b29ff375e83p-945, 0x1.21bd19407d3a8p-939 },
+ { 0x1.bd5a7cbaf896dp-946, 0x1.7ad97206eb3e9p-940 },
+ { 0x1.230b0dec754dap-946, 0x1.ef4e6059f1fe4p-941 },
+ { 0x1.7c5a693980a4p-947, 0x1.43bdb9112e65bp-941 },
+ { 0x1.f10221f87a1cap-948, 0x1.a7278c0b2c815p-942 },
+ { 0x1.44ae6c097e3b8p-948, 0x1.148391a9b5b7p-942 },
+ { 0x1.a8288818abb4p-949, 0x1.69563388e87eep-943 },
+},
+};
diff --git a/sysdeps/aarch64/fpu/erfc_sve.c b/sysdeps/aarch64/fpu/erfc_sve.c
new file mode 100644
index 0000000000..c17d3e4484
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfc_sve.c
@@ -0,0 +1,167 @@
+/* Double-precision vector (SVE) erfc function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+#include "vecmath_config.h"
+
+static const struct data
+{
+ uint64_t off_idx, off_arr;
+ double max, shift;
+ double p20, p40, p41, p42;
+ double p51, p52;
+ double q5, r5;
+ double q6, r6;
+ double q7, r7;
+ double q8, r8;
+ double q9, r9;
+ uint64_t table_scale;
+} data = {
+ /* Set an offset so the range of the index used for lookup is 3487, and it
+ can be clamped using a saturated add on an offset index.
+ Index offset is 0xffffffffffffffff - asuint64(shift) - 3487. */
+ .off_idx = 0xbd3ffffffffff260,
+ .off_arr = 0xfffffffffffff260, /* 0xffffffffffffffff - 3487. */
+ .max = 0x1.b3ep+4, /* 3487/128. */
+ .shift = 0x1p45,
+ .table_scale = 0x37f0000000000000, /* asuint64(0x1p-128). */
+ .p20 = 0x1.5555555555555p-2, /* 1/3, used to compute 2/3 and 1/6. */
+ .p40 = -0x1.999999999999ap-4, /* 1/10. */
+ .p41 = -0x1.999999999999ap-2, /* 2/5. */
+ .p42 = 0x1.1111111111111p-3, /* 2/15. */
+ .p51 = -0x1.c71c71c71c71cp-3, /* 2/9. */
+ .p52 = 0x1.6c16c16c16c17p-5, /* 2/45. */
+ /* Qi = (i+1) / i, for i = 5, ..., 9. */
+ .q5 = 0x1.3333333333333p0,
+ .q6 = 0x1.2aaaaaaaaaaabp0,
+ .q7 = 0x1.2492492492492p0,
+ .q8 = 0x1.2p0,
+ .q9 = 0x1.1c71c71c71c72p0,
+ /* Ri = -2 * i / ((i+1)*(i+2)), for i = 5, ..., 9. */
+ .r5 = -0x1.e79e79e79e79ep-3,
+ .r6 = -0x1.b6db6db6db6dbp-3,
+ .r7 = -0x1.8e38e38e38e39p-3,
+ .r8 = -0x1.6c16c16c16c17p-3,
+ .r9 = -0x1.4f2094f2094f2p-3,
+};
+
+/* Optimized double-precision vector erfc(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/128.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erfc(x) ~ erfc(r) - scale * d * poly(r, d), with
+
+ poly(r, d) = 1 - r d + (2/3 r^2 - 1/3) d^2 - r (1/3 r^2 - 1/2) d^3
+ + (2/15 r^4 - 2/5 r^2 + 1/10) d^4
+ - r * (2/45 r^4 - 2/9 r^2 + 1/6) d^5
+ + p6(r) d^6 + ... + p10(r) d^10
+
+ Polynomials p6(r) to p10(r) are computed using recurrence relation
+
+ 2(i+1)p_i + 2r(i+2)p_{i+1} + (i+2)(i+3)p_{i+2} = 0,
+ with p0 = 1, and p1(r) = -r.
+
+ Values of erfc(r) and scale are read from lookup tables. Stored values
+ are scaled to avoid hitting the subnormal range.
+
+ Note that for x < 0, erfc(x) = 2.0 - erfc(-x).
+
+ Maximum measured error: 1.71 ULP
+ _ZGVsMxv_erfc(0x1.46cfe976733p+4) got 0x1.e15fcbea3e7afp-608
+ want 0x1.e15fcbea3e7adp-608. */
+svfloat64_t SV_NAME_D1 (erfc) (svfloat64_t x, const svbool_t pg)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+ svfloat64_t a = svabs_x (pg, x);
+
+ /* Clamp input at |x| <= 3487/128. */
+ a = svmin_x (pg, a, dat->max);
+
+ /* Reduce x to the nearest multiple of 1/128. */
+ svfloat64_t shift = sv_f64 (dat->shift);
+ svfloat64_t z = svadd_x (pg, a, shift);
+
+ /* Saturate index for the NaN case. */
+ svuint64_t i = svqadd (svreinterpret_u64 (z), dat->off_idx);
+
+ /* Lookup erfc(r) and 2/sqrt(pi)*exp(-r^2) in tables. */
+ i = svadd_x (pg, i, i);
+ const float64_t *p = &__erfc_data.tab[0].erfc - 2 * dat->off_arr;
+ svfloat64_t erfcr = svld1_gather_index (pg, p, i);
+ svfloat64_t scale = svld1_gather_index (pg, p + 1, i);
+
+ /* erfc(x) ~ erfc(r) - scale * d * poly(r, d). */
+ svfloat64_t r = svsub_x (pg, z, shift);
+ svfloat64_t d = svsub_x (pg, a, r);
+ svfloat64_t d2 = svmul_x (pg, d, d);
+ svfloat64_t r2 = svmul_x (pg, r, r);
+
+ /* poly (d, r) = 1 + p1(r) * d + p2(r) * d^2 + ... + p9(r) * d^9. */
+ svfloat64_t p1 = r;
+ svfloat64_t third = sv_f64 (dat->p20);
+ svfloat64_t twothird = svmul_x (pg, third, 2.0);
+ svfloat64_t sixth = svmul_x (pg, third, 0.5);
+ svfloat64_t p2 = svmls_x (pg, third, r2, twothird);
+ svfloat64_t p3 = svmad_x (pg, r2, third, -0.5);
+ p3 = svmul_x (pg, r, p3);
+ svfloat64_t p4 = svmla_x (pg, sv_f64 (dat->p41), r2, dat->p42);
+ p4 = svmls_x (pg, sv_f64 (dat->p40), r2, p4);
+ svfloat64_t p5 = svmla_x (pg, sv_f64 (dat->p51), r2, dat->p52);
+ p5 = svmla_x (pg, sixth, r2, p5);
+ p5 = svmul_x (pg, r, p5);
+ /* Compute p_i using recurrence relation:
+ p_{i+2} = (p_i + r * Q_{i+1} * p_{i+1}) * R_{i+1}. */
+ svfloat64_t qr5 = svld1rq (svptrue_b64 (), &dat->q5);
+ svfloat64_t qr6 = svld1rq (svptrue_b64 (), &dat->q6);
+ svfloat64_t qr7 = svld1rq (svptrue_b64 (), &dat->q7);
+ svfloat64_t qr8 = svld1rq (svptrue_b64 (), &dat->q8);
+ svfloat64_t qr9 = svld1rq (svptrue_b64 (), &dat->q9);
+ svfloat64_t p6 = svmla_x (pg, p4, p5, svmul_lane (r, qr5, 0));
+ p6 = svmul_lane (p6, qr5, 1);
+ svfloat64_t p7 = svmla_x (pg, p5, p6, svmul_lane (r, qr6, 0));
+ p7 = svmul_lane (p7, qr6, 1);
+ svfloat64_t p8 = svmla_x (pg, p6, p7, svmul_lane (r, qr7, 0));
+ p8 = svmul_lane (p8, qr7, 1);
+ svfloat64_t p9 = svmla_x (pg, p7, p8, svmul_lane (r, qr8, 0));
+ p9 = svmul_lane (p9, qr8, 1);
+ svfloat64_t p10 = svmla_x (pg, p8, p9, svmul_lane (r, qr9, 0));
+ p10 = svmul_lane (p10, qr9, 1);
+ /* Compute polynomial in d using pairwise Horner scheme. */
+ svfloat64_t p90 = svmla_x (pg, p9, d, p10);
+ svfloat64_t p78 = svmla_x (pg, p7, d, p8);
+ svfloat64_t p56 = svmla_x (pg, p5, d, p6);
+ svfloat64_t p34 = svmla_x (pg, p3, d, p4);
+ svfloat64_t p12 = svmla_x (pg, p1, d, p2);
+ svfloat64_t y = svmla_x (pg, p78, d2, p90);
+ y = svmla_x (pg, p56, d2, y);
+ y = svmla_x (pg, p34, d2, y);
+ y = svmla_x (pg, p12, d2, y);
+
+ y = svmls_x (pg, erfcr, scale, svmls_x (pg, d, d2, y));
+
+ /* Offset equals 2.0 if sign, else 0.0. */
+ svuint64_t sign = svand_x (pg, svreinterpret_u64 (x), 0x8000000000000000);
+ svfloat64_t off = svreinterpret_f64 (svlsr_x (pg, sign, 1));
+ /* Handle sign and scale back in a single fma. */
+ svfloat64_t fac = svreinterpret_f64 (svorr_x (pg, sign, dat->table_scale));
+
+ return svmla_x (pg, off, fac, y);
+}
diff --git a/sysdeps/aarch64/fpu/erfcf_advsimd.c b/sysdeps/aarch64/fpu/erfcf_advsimd.c
new file mode 100644
index 0000000000..30b9e48dd4
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfcf_advsimd.c
@@ -0,0 +1,170 @@
+/* Single-precision vector (Advanced SIMD) erfc function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "v_math.h"
+
+static const struct data
+{
+ uint32x4_t offset, table_scale;
+ float32x4_t max, shift;
+ float32x4_t coeffs, third, two_over_five, tenth;
+#if WANT_SIMD_EXCEPT
+ float32x4_t uflow_bound;
+#endif
+
+} data = {
+ /* Set an offset so the range of the index used for lookup is 644, and it can
+ be clamped using a saturated add. */
+ .offset = V4 (0xb7fffd7b), /* 0xffffffff - asuint(shift) - 644. */
+ .table_scale = V4 (0x28000000 << 1), /* asuint (2^-47) << 1. */
+ .max = V4 (10.0625f), /* 10 + 1/16 = 644/64. */
+ .shift = V4 (0x1p17f),
+ /* Store 1/3, 2/3 and 2/15 in a single register for use with indexed muls and
+ fmas. */
+ .coeffs = (float32x4_t){ 0x1.555556p-2f, 0x1.555556p-1f, 0x1.111112p-3f, 0 },
+ .third = V4 (0x1.555556p-2f),
+ .two_over_five = V4 (-0x1.99999ap-2f),
+ .tenth = V4 (-0x1.99999ap-4f),
+#if WANT_SIMD_EXCEPT
+ .uflow_bound = V4 (0x1.2639cp+3f),
+#endif
+};
+
+#define TinyBound 0x41000000 /* 0x1p-62f << 1. */
+#define Thres 0xbe000000 /* asuint(infinity) << 1 - TinyBound. */
+#define Off 0xfffffd7b /* 0xffffffff - 644. */
+
+struct entry
+{
+ float32x4_t erfc;
+ float32x4_t scale;
+};
+
+static inline struct entry
+lookup (uint32x4_t i)
+{
+ struct entry e;
+ float64_t t0 = *((float64_t *) (__erfcf_data.tab - Off + i[0]));
+ float64_t t1 = *((float64_t *) (__erfcf_data.tab - Off + i[1]));
+ float64_t t2 = *((float64_t *) (__erfcf_data.tab - Off + i[2]));
+ float64_t t3 = *((float64_t *) (__erfcf_data.tab - Off + i[3]));
+ float32x4_t e1 = vreinterpretq_f32_f64 ((float64x2_t){ t0, t1 });
+ float32x4_t e2 = vreinterpretq_f32_f64 ((float64x2_t){ t2, t3 });
+ e.erfc = vuzp1q_f32 (e1, e2);
+ e.scale = vuzp2q_f32 (e1, e2);
+ return e;
+}
+
+#if WANT_SIMD_EXCEPT
+static float32x4_t VPCS_ATTR NOINLINE
+special_case (float32x4_t x, float32x4_t y, uint32x4_t cmp)
+{
+ return v_call_f32 (erfcf, x, y, cmp);
+}
+#endif
+
+/* Optimized single-precision vector erfcf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/64.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erfc(x) ~ erfc(r) - scale * d * poly(r, d), with
+
+ poly(r, d) = 1 - r d + (2/3 r^2 - 1/3) d^2 - r (1/3 r^2 - 1/2) d^3
+ + (2/15 r^4 - 2/5 r^2 + 1/10) d^4
+
+ Values of erfc(r) and scale are read from lookup tables. Stored values
+ are scaled to avoid hitting the subnormal range.
+
+ Note that for x < 0, erfc(x) = 2.0 - erfc(-x).
+ Maximum error: 1.63 ULP (~1.0 ULP for x < 0.0).
+ _ZGVnN4v_erfcf(0x1.1dbf7ap+3) got 0x1.f51212p-120
+ want 0x1.f51216p-120. */
+VPCS_ATTR
+float32x4_t NOINLINE V_NAME_F1 (erfc) (float32x4_t x)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+#if WANT_SIMD_EXCEPT
+ /* |x| < 2^-62. Avoid fabs by left-shifting by 1. */
+ uint32x4_t ix = vreinterpretq_u32_f32 (x);
+ uint32x4_t cmp = vcltq_u32 (vaddq_u32 (ix, ix), v_u32 (TinyBound));
+ /* x >= ~9.19 (into subnormal case and uflow case). Comparison is done in
+ integer domain to avoid raising exceptions in presence of nans. */
+ uint32x4_t uflow = vcgeq_s32 (vreinterpretq_s32_f32 (x),
+ vreinterpretq_s32_f32 (dat->uflow_bound));
+ cmp = vorrq_u32 (cmp, uflow);
+ float32x4_t xm = x;
+ /* If any lanes are special, mask them with 0 and retain a copy of x to allow
+ special case handler to fix special lanes later. This is only necessary if
+ fenv exceptions are to be triggered correctly. */
+ if (__glibc_unlikely (v_any_u32 (cmp)))
+ x = v_zerofy_f32 (x, cmp);
+#endif
+
+ float32x4_t a = vabsq_f32 (x);
+ a = vminq_f32 (a, dat->max);
+
+ /* Lookup erfc(r) and scale(r) in tables, e.g. set erfc(r) to 0 and scale to
+ 2/sqrt(pi), when x reduced to r = 0. */
+ float32x4_t shift = dat->shift;
+ float32x4_t z = vaddq_f32 (a, shift);
+
+ /* Clamp index to a range of 644. A naive approach would use a subtract and
+ min. Instead we offset the table address and the index, then use a
+ saturating add. */
+ uint32x4_t i = vqaddq_u32 (vreinterpretq_u32_f32 (z), dat->offset);
+
+ struct entry e = lookup (i);
+
+ /* erfc(x) ~ erfc(r) - scale * d * poly(r, d). */
+ float32x4_t r = vsubq_f32 (z, shift);
+ float32x4_t d = vsubq_f32 (a, r);
+ float32x4_t d2 = vmulq_f32 (d, d);
+ float32x4_t r2 = vmulq_f32 (r, r);
+
+ float32x4_t p1 = r;
+ float32x4_t p2 = vfmsq_laneq_f32 (dat->third, r2, dat->coeffs, 1);
+ float32x4_t p3
+ = vmulq_f32 (r, vfmaq_laneq_f32 (v_f32 (-0.5), r2, dat->coeffs, 0));
+ float32x4_t p4 = vfmaq_laneq_f32 (dat->two_over_five, r2, dat->coeffs, 2);
+ p4 = vfmsq_f32 (dat->tenth, r2, p4);
+
+ float32x4_t y = vfmaq_f32 (p3, d, p4);
+ y = vfmaq_f32 (p2, d, y);
+ y = vfmaq_f32 (p1, d, y);
+ y = vfmsq_f32 (e.erfc, e.scale, vfmsq_f32 (d, d2, y));
+
+ /* Offset equals 2.0f if sign, else 0.0f. */
+ uint32x4_t sign = vshrq_n_u32 (vreinterpretq_u32_f32 (x), 31);
+ float32x4_t off = vreinterpretq_f32_u32 (vshlq_n_u32 (sign, 30));
+ /* Copy sign and scale back in a single fma. Since the bit patterns do not
+ overlap, then logical or and addition are equivalent here. */
+ float32x4_t fac = vreinterpretq_f32_u32 (
+ vsraq_n_u32 (vshlq_n_u32 (sign, 31), dat->table_scale, 1));
+
+#if WANT_SIMD_EXCEPT
+ if (__glibc_unlikely (v_any_u32 (cmp)))
+ return special_case (xm, vfmaq_f32 (off, fac, y), cmp);
+#endif
+
+ return vfmaq_f32 (off, fac, y);
+}
+libmvec_hidden_def (V_NAME_F1 (erfc))
+HALF_WIDTH_ALIAS_F1 (erfc)
diff --git a/sysdeps/aarch64/fpu/erfcf_data.c b/sysdeps/aarch64/fpu/erfcf_data.c
new file mode 100644
index 0000000000..77fb889a78
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfcf_data.c
@@ -0,0 +1,676 @@
+/* Table for Advanced SIMD erfcf
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "vecmath_config.h"
+
+/* Lookup table used in erfcf.
+ For each possible rounded input r (multiples of 1/64), between
+ r = 0.0 and r = 10.0625 (645 values):
+ - the first entry __erfcf_data.tab.erfc contains the values of erfc(r),
+ - the second entry __erfcf_data.tab.scale contains the values of
+ 2/sqrt(pi)*exp(-r^2). Both values may go into subnormal range, therefore
+ they are scaled by a large enough value 2^47 (fits in 8 bits). */
+const struct erfcf_data __erfcf_data = {
+ .tab = { { 0x1p47, 0x1.20dd76p47 },
+ { 0x1.f6f944p46, 0x1.20cb68p47 },
+ { 0x1.edf3aap46, 0x1.209546p47 },
+ { 0x1.e4f05p46, 0x1.203b26p47 },
+ { 0x1.dbf056p46, 0x1.1fbd28p47 },
+ { 0x1.d2f4dcp46, 0x1.1f1b7ap47 },
+ { 0x1.c9fefep46, 0x1.1e565cp47 },
+ { 0x1.c10fd4p46, 0x1.1d6e14p47 },
+ { 0x1.b8287ap46, 0x1.1c62fap47 },
+ { 0x1.af4ap46, 0x1.1b3572p47 },
+ { 0x1.a6757ep46, 0x1.19e5eap47 },
+ { 0x1.9dabfcp46, 0x1.1874dep47 },
+ { 0x1.94ee88p46, 0x1.16e2d8p47 },
+ { 0x1.8c3e24p46, 0x1.153068p47 },
+ { 0x1.839bd6p46, 0x1.135e3p47 },
+ { 0x1.7b0894p46, 0x1.116cd8p47 },
+ { 0x1.728558p46, 0x1.0f5d16p47 },
+ { 0x1.6a1312p46, 0x1.0d2fa6p47 },
+ { 0x1.61b2acp46, 0x1.0ae55p47 },
+ { 0x1.596508p46, 0x1.087ee4p47 },
+ { 0x1.512b06p46, 0x1.05fd3ep47 },
+ { 0x1.49057ap46, 0x1.03614p47 },
+ { 0x1.40f536p46, 0x1.00abdp47 },
+ { 0x1.38fbp46, 0x1.fbbbbep46 },
+ { 0x1.311796p46, 0x1.f5f0cep46 },
+ { 0x1.294bb4p46, 0x1.eff8c4p46 },
+ { 0x1.21980ap46, 0x1.e9d5a8p46 },
+ { 0x1.19fd3ep46, 0x1.e38988p46 },
+ { 0x1.127bf2p46, 0x1.dd167cp46 },
+ { 0x1.0b14bcp46, 0x1.d67ea2p46 },
+ { 0x1.03c82ap46, 0x1.cfc41ep46 },
+ { 0x1.f92d8cp45, 0x1.c8e91cp46 },
+ { 0x1.eb0214p45, 0x1.c1efcap46 },
+ { 0x1.dd0edap45, 0x1.bada5ap46 },
+ { 0x1.cf54b4p45, 0x1.b3aafcp46 },
+ { 0x1.c1d46ap45, 0x1.ac63e8p46 },
+ { 0x1.b48eaep45, 0x1.a5074ep46 },
+ { 0x1.a78428p45, 0x1.9d9762p46 },
+ { 0x1.9ab566p45, 0x1.96165p46 },
+ { 0x1.8e22eap45, 0x1.8e8646p46 },
+ { 0x1.81cd24p45, 0x1.86e96ap46 },
+ { 0x1.75b47p45, 0x1.7f41dcp46 },
+ { 0x1.69d91ep45, 0x1.7791b8p46 },
+ { 0x1.5e3b66p45, 0x1.6fdb12p46 },
+ { 0x1.52db78p45, 0x1.681ff2p46 },
+ { 0x1.47b96ep45, 0x1.60625cp46 },
+ { 0x1.3cd554p45, 0x1.58a446p46 },
+ { 0x1.322f26p45, 0x1.50e79ep46 },
+ { 0x1.27c6d2p45, 0x1.492e42p46 },
+ { 0x1.1d9c34p45, 0x1.417a0cp46 },
+ { 0x1.13af1ep45, 0x1.39ccc2p46 },
+ { 0x1.09ff5p45, 0x1.32281ep46 },
+ { 0x1.008c8p45, 0x1.2a8dcep46 },
+ { 0x1.eeaca8p44, 0x1.22ff72p46 },
+ { 0x1.dcb8cap44, 0x1.1b7e98p46 },
+ { 0x1.cb3c86p44, 0x1.140cc4p46 },
+ { 0x1.ba36dap44, 0x1.0cab62p46 },
+ { 0x1.a9a6bap44, 0x1.055bd6p46 },
+ { 0x1.998afap44, 0x1.fc3ee6p45 },
+ { 0x1.89e25ep44, 0x1.edeeeep45 },
+ { 0x1.7aab98p44, 0x1.dfca26p45 },
+ { 0x1.6be542p44, 0x1.d1d2dp45 },
+ { 0x1.5d8decp44, 0x1.c40b08p45 },
+ { 0x1.4fa40ep44, 0x1.b674c8p45 },
+ { 0x1.422616p44, 0x1.a911fp45 },
+ { 0x1.351262p44, 0x1.9be438p45 },
+ { 0x1.28674p44, 0x1.8eed36p45 },
+ { 0x1.1c22f8p44, 0x1.822e66p45 },
+ { 0x1.1043c2p44, 0x1.75a91ap45 },
+ { 0x1.04c7cap44, 0x1.695e8cp45 },
+ { 0x1.f35a72p43, 0x1.5d4fd4p45 },
+ { 0x1.dde456p43, 0x1.517de6p45 },
+ { 0x1.c9296cp43, 0x1.45e99cp45 },
+ { 0x1.b525d6p43, 0x1.3a93b2p45 },
+ { 0x1.a1d5a6p43, 0x1.2f7cc4p45 },
+ { 0x1.8f34eap43, 0x1.24a554p45 },
+ { 0x1.7d3fa6p43, 0x1.1a0dc6p45 },
+ { 0x1.6bf1dcp43, 0x1.0fb662p45 },
+ { 0x1.5b4784p43, 0x1.059f5ap45 },
+ { 0x1.4b3c98p43, 0x1.f79184p44 },
+ { 0x1.3bcd14p43, 0x1.e4653p44 },
+ { 0x1.2cf4eep43, 0x1.d1b982p44 },
+ { 0x1.1eb024p43, 0x1.bf8e1cp44 },
+ { 0x1.10fab8p43, 0x1.ade26cp44 },
+ { 0x1.03d0acp43, 0x1.9cb5bep44 },
+ { 0x1.ee5c18p42, 0x1.8c0732p44 },
+ { 0x1.d61dd6p42, 0x1.7bd5c8p44 },
+ { 0x1.bedec8p42, 0x1.6c2056p44 },
+ { 0x1.a8973cp42, 0x1.5ce596p44 },
+ { 0x1.933f9p42, 0x1.4e241ep44 },
+ { 0x1.7ed03ap42, 0x1.3fda6cp44 },
+ { 0x1.6b41ccp42, 0x1.3206dcp44 },
+ { 0x1.588cf2p42, 0x1.24a7b8p44 },
+ { 0x1.46aa72p42, 0x1.17bb2cp44 },
+ { 0x1.359332p42, 0x1.0b3f52p44 },
+ { 0x1.254038p42, 0x1.fe646p43 },
+ { 0x1.15aaa8p42, 0x1.e72372p43 },
+ { 0x1.06cbcap42, 0x1.d0b7ap43 },
+ { 0x1.f13a04p41, 0x1.bb1c98p43 },
+ { 0x1.d62fbep41, 0x1.a64de6p43 },
+ { 0x1.bc6c1ep41, 0x1.92470ap43 },
+ { 0x1.a3e2ccp41, 0x1.7f036cp43 },
+ { 0x1.8c87b8p41, 0x1.6c7e64p43 },
+ { 0x1.764f2p41, 0x1.5ab342p43 },
+ { 0x1.612d8ap41, 0x1.499d48p43 },
+ { 0x1.4d17cap41, 0x1.3937b2p43 },
+ { 0x1.3a03p41, 0x1.297dbap43 },
+ { 0x1.27e498p41, 0x1.1a6a96p43 },
+ { 0x1.16b24cp41, 0x1.0bf97ep43 },
+ { 0x1.066222p41, 0x1.fc4b5ep42 },
+ { 0x1.edd4d2p40, 0x1.e1d4dp42 },
+ { 0x1.d08382p40, 0x1.c885ep42 },
+ { 0x1.b4be2p40, 0x1.b0553p42 },
+ { 0x1.9a7316p40, 0x1.99397ap42 },
+ { 0x1.81915cp40, 0x1.83298ep42 },
+ { 0x1.6a088p40, 0x1.6e1c58p42 },
+ { 0x1.53c89ep40, 0x1.5a08e8p42 },
+ { 0x1.3ec25ep40, 0x1.46e66cp42 },
+ { 0x1.2ae6fap40, 0x1.34ac36p42 },
+ { 0x1.18282ep40, 0x1.2351c2p42 },
+ { 0x1.067844p40, 0x1.12ceb4p42 },
+ { 0x1.eb940ep39, 0x1.031ad6p42 },
+ { 0x1.cc2186p39, 0x1.e85c44p41 },
+ { 0x1.ae808cp39, 0x1.cc018p41 },
+ { 0x1.9299bp39, 0x1.b1160ap41 },
+ { 0x1.785674p39, 0x1.978ae8p41 },
+ { 0x1.5fa14ap39, 0x1.7f5188p41 },
+ { 0x1.486586p39, 0x1.685bb6p41 },
+ { 0x1.328f5ep39, 0x1.529b9ep41 },
+ { 0x1.1e0be6p39, 0x1.3e03d8p41 },
+ { 0x1.0ac8fcp39, 0x1.2a875cp41 },
+ { 0x1.f16aaep38, 0x1.181984p41 },
+ { 0x1.cf80d4p38, 0x1.06ae14p41 },
+ { 0x1.afb4e2p38, 0x1.ec7262p40 },
+ { 0x1.91e8bep38, 0x1.cd5ecap40 },
+ { 0x1.75ffb4p38, 0x1.b00b38p40 },
+ { 0x1.5bde72p38, 0x1.94624ep40 },
+ { 0x1.436af4p38, 0x1.7a4f6ap40 },
+ { 0x1.2c8c7ap38, 0x1.61beaep40 },
+ { 0x1.172b7ap38, 0x1.4a9cf6p40 },
+ { 0x1.033198p38, 0x1.34d7dcp40 },
+ { 0x1.e11332p37, 0x1.205dacp40 },
+ { 0x1.be3ebp37, 0x1.0d1d6ap40 },
+ { 0x1.9dbf72p37, 0x1.f60d8ap39 },
+ { 0x1.7f714p37, 0x1.d4143ap39 },
+ { 0x1.6331cap37, 0x1.b430ecp39 },
+ { 0x1.48e09cp37, 0x1.9646f4p39 },
+ { 0x1.305ef8p37, 0x1.7a3adep39 },
+ { 0x1.198fd6p37, 0x1.5ff276p39 },
+ { 0x1.0457c6p37, 0x1.4754acp39 },
+ { 0x1.e139bcp36, 0x1.30499cp39 },
+ { 0x1.bc8d52p36, 0x1.1aba78p39 },
+ { 0x1.9a7c3p36, 0x1.06918cp39 },
+ { 0x1.7adadep36, 0x1.e77448p38 },
+ { 0x1.5d806ap36, 0x1.c4412cp38 },
+ { 0x1.424642p36, 0x1.a36454p38 },
+ { 0x1.290826p36, 0x1.84ba3p38 },
+ { 0x1.11a3f8p36, 0x1.6821p38 },
+ { 0x1.f7f358p35, 0x1.4d78bcp38 },
+ { 0x1.cfd652p35, 0x1.34a306p38 },
+ { 0x1.aab85ap35, 0x1.1d8318p38 },
+ { 0x1.88647p35, 0x1.07fdb4p38 },
+ { 0x1.68a8e4p35, 0x1.e7f232p37 },
+ { 0x1.4b5726p35, 0x1.c2b9dp37 },
+ { 0x1.30439cp35, 0x1.a02436p37 },
+ { 0x1.174578p35, 0x1.8005fp37 },
+ { 0x1.003692p35, 0x1.6235fcp37 },
+ { 0x1.d5e678p34, 0x1.468daep37 },
+ { 0x1.aeb442p34, 0x1.2ce898p37 },
+ { 0x1.8a9848p34, 0x1.15246ep37 },
+ { 0x1.695876p34, 0x1.fe41cep36 },
+ { 0x1.4abea2p34, 0x1.d57f52p36 },
+ { 0x1.2e984ep34, 0x1.afc85ep36 },
+ { 0x1.14b676p34, 0x1.8ce75ep36 },
+ { 0x1.f9daap33, 0x1.6caa0ep36 },
+ { 0x1.ce283ap33, 0x1.4ee142p36 },
+ { 0x1.a609f8p33, 0x1.3360ccp36 },
+ { 0x1.81396ap33, 0x1.19ff46p36 },
+ { 0x1.5f7524p33, 0x1.0295fp36 },
+ { 0x1.40806ep33, 0x1.da011p35 },
+ { 0x1.2422eep33, 0x1.b23a5ap35 },
+ { 0x1.0a286p33, 0x1.8d986ap35 },
+ { 0x1.e4c0bp32, 0x1.6be022p35 },
+ { 0x1.b93bf4p32, 0x1.4cda54p35 },
+ { 0x1.916f7cp32, 0x1.30539p35 },
+ { 0x1.6d0e7p32, 0x1.161be4p35 },
+ { 0x1.4bd1cp32, 0x1.fc0d56p34 },
+ { 0x1.2d77bep32, 0x1.cfd4a6p34 },
+ { 0x1.11c3bep32, 0x1.a74068p34 },
+ { 0x1.f0fb86p31, 0x1.8208bcp34 },
+ { 0x1.c2e43ep31, 0x1.5feadap34 },
+ { 0x1.98e254p31, 0x1.40a8c2p34 },
+ { 0x1.729df6p31, 0x1.2408eap34 },
+ { 0x1.4fc63cp31, 0x1.09d5f8p34 },
+ { 0x1.3010aap31, 0x1.e3bcf4p33 },
+ { 0x1.1338b8p31, 0x1.b7e946p33 },
+ { 0x1.f1fecp30, 0x1.8fdc1cp33 },
+ { 0x1.c2556ap30, 0x1.6b4702p33 },
+ { 0x1.970b06p30, 0x1.49e178p33 },
+ { 0x1.6fbddep30, 0x1.2b6876p33 },
+ { 0x1.4c144ep30, 0x1.0f9e1cp33 },
+ { 0x1.2bbc1ep30, 0x1.ec929ap32 },
+ { 0x1.0e69f2p30, 0x1.be6abcp32 },
+ { 0x1.e7b188p29, 0x1.94637ep32 },
+ { 0x1.b792bcp29, 0x1.6e2368p32 },
+ { 0x1.8c03d2p29, 0x1.4b581cp32 },
+ { 0x1.649b02p29, 0x1.2bb5ccp32 },
+ { 0x1.40f794p29, 0x1.0ef6c4p32 },
+ { 0x1.20c13p29, 0x1.e9b5e8p31 },
+ { 0x1.03a72ap29, 0x1.ba4f04p31 },
+ { 0x1.d2bfc6p28, 0x1.8f4cccp31 },
+ { 0x1.a35068p28, 0x1.684c22p31 },
+ { 0x1.7885cep28, 0x1.44f21ep31 },
+ { 0x1.51f06ap28, 0x1.24eb72p31 },
+ { 0x1.2f2aaap28, 0x1.07ebd2p31 },
+ { 0x1.0fd816p28, 0x1.db5adp30 },
+ { 0x1.e7493p27, 0x1.abe09ep30 },
+ { 0x1.b48774p27, 0x1.80f43ap30 },
+ { 0x1.86e006p27, 0x1.5a2aep30 },
+ { 0x1.5dd4bp27, 0x1.37231p30 },
+ { 0x1.38f2e8p27, 0x1.1783cep30 },
+ { 0x1.17d2c6p27, 0x1.f5f7d8p29 },
+ { 0x1.f42c18p26, 0x1.c282cep29 },
+ { 0x1.beceb2p26, 0x1.94219cp29 },
+ { 0x1.8ef2aap26, 0x1.6a5972p29 },
+ { 0x1.640bf6p26, 0x1.44ba86p29 },
+ { 0x1.3d9be6p26, 0x1.22df2ap29 },
+ { 0x1.1b2fe4p26, 0x1.046aeap29 },
+ { 0x1.f8c0c2p25, 0x1.d21398p28 },
+ { 0x1.c19fa8p25, 0x1.a0df1p28 },
+ { 0x1.90538cp25, 0x1.74adc8p28 },
+ { 0x1.6443fep25, 0x1.4d0232p28 },
+ { 0x1.3ce784p25, 0x1.296a7p28 },
+ { 0x1.19c232p25, 0x1.097f62p28 },
+ { 0x1.f4c8c4p24, 0x1.d9c736p27 },
+ { 0x1.bcd30ep24, 0x1.a6852cp27 },
+ { 0x1.8aee4cp24, 0x1.789fb8p27 },
+ { 0x1.5e77b6p24, 0x1.4f8c96p27 },
+ { 0x1.36dcf2p24, 0x1.2acee2p27 },
+ { 0x1.139a7cp24, 0x1.09f5dp27 },
+ { 0x1.e8747p23, 0x1.d9371ep26 },
+ { 0x1.b0a44ap23, 0x1.a4c89ep26 },
+ { 0x1.7f064ap23, 0x1.75fa8ep26 },
+ { 0x1.52efep23, 0x1.4c37cp26 },
+ { 0x1.2bc82ap23, 0x1.26f9ep26 },
+ { 0x1.09064p23, 0x1.05c804p26 },
+ { 0x1.d45f16p22, 0x1.d06ad6p25 },
+ { 0x1.9dacb2p22, 0x1.9bc0ap25 },
+ { 0x1.6d3126p22, 0x1.6ce1aap25 },
+ { 0x1.423d14p22, 0x1.43302cp25 },
+ { 0x1.1c33cep22, 0x1.1e1e86p25 },
+ { 0x1.f512dep21, 0x1.fa5b5p24 },
+ { 0x1.b9823cp21, 0x1.bfd756p24 },
+ { 0x1.84d6fep21, 0x1.8be4f8p24 },
+ { 0x1.564a92p21, 0x1.5dcd66p24 },
+ { 0x1.2d2c0ap21, 0x1.34ecf8p24 },
+ { 0x1.08ddd2p21, 0x1.10b148p24 },
+ { 0x1.d1a75p20, 0x1.e12eep23 },
+ { 0x1.99218cp20, 0x1.a854eap23 },
+ { 0x1.674c6ap20, 0x1.7603bap23 },
+ { 0x1.3b62b6p20, 0x1.4980ccp23 },
+ { 0x1.14b54p20, 0x1.2225b2p23 },
+ { 0x1.e55102p19, 0x1.febc1p22 },
+ { 0x1.a964eep19, 0x1.c14b22p22 },
+ { 0x1.74b17ap19, 0x1.8b0cfcp22 },
+ { 0x1.465daap19, 0x1.5b2fe6p22 },
+ { 0x1.1da944p19, 0x1.30f93cp22 },
+ { 0x1.f3d41p18, 0x1.0bc30cp22 },
+ { 0x1.b512a2p18, 0x1.d5f3a8p21 },
+ { 0x1.7e03b2p18, 0x1.9c3518p21 },
+ { 0x1.4dbb98p18, 0x1.6961b8p21 },
+ { 0x1.236a1ap18, 0x1.3cab14p21 },
+ { 0x1.fcae94p17, 0x1.155a0ap21 },
+ { 0x1.bbc1ap17, 0x1.e5989p20 },
+ { 0x1.82eedcp17, 0x1.a8e406p20 },
+ { 0x1.5139a6p17, 0x1.7397c6p20 },
+ { 0x1.25c354p17, 0x1.44d26ep20 },
+ { 0x1.ff8f84p16, 0x1.1bcca4p20 },
+ { 0x1.bd3474p16, 0x1.efac52p19 },
+ { 0x1.834586p16, 0x1.b0a68ap19 },
+ { 0x1.50b75cp16, 0x1.7974e8p19 },
+ { 0x1.249ef2p16, 0x1.4924a8p19 },
+ { 0x1.fc5b88p15, 0x1.1edfa4p19 },
+ { 0x1.b95ceep15, 0x1.f3d218p18 },
+ { 0x1.7f03bap15, 0x1.b334fap18 },
+ { 0x1.4c389cp15, 0x1.7ac2d8p18 },
+ { 0x1.2006aep15, 0x1.4979acp18 },
+ { 0x1.f32eap14, 0x1.1e767cp18 },
+ { 0x1.b05cfep14, 0x1.f1e352p17 },
+ { 0x1.764f46p14, 0x1.b0778cp17 },
+ { 0x1.43e56cp14, 0x1.77756ep17 },
+ { 0x1.18238p14, 0x1.45ce66p17 },
+ { 0x1.e45a98p13, 0x1.1a95p17 },
+ { 0x1.a284ccp13, 0x1.e9f2p16 },
+ { 0x1.697596p13, 0x1.a887bep16 },
+ { 0x1.3807acp13, 0x1.6fab64p16 },
+ { 0x1.0d3b36p13, 0x1.3e44e4p16 },
+ { 0x1.d0624p12, 0x1.135f28p16 },
+ { 0x1.904e0cp12, 0x1.dc479ep15 },
+ { 0x1.58e72ap12, 0x1.9baed4p15 },
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+ { 0x1.7d62a2p-87, 0x1.c5e534p-83 },
+ { 0x1.1b2abcp-87, 0x1.518db2p-83 },
+ { 0x1.a4480ep-88, 0x1.f5d1c6p-84 },
+ { 0x1.37be42p-88, 0x1.74d45ap-84 },
+ { 0x1.ce3ee4p-89, 0x1.14dc4ap-84 },
+ { 0x1.568986p-89, 0x1.9afd0ep-85 },
+ { 0x1.fb69c6p-90, 0x1.30e632p-85 },
+ { 0x1.77a47ep-90, 0x1.c42b48p-86 },
+ { 0x1.15f4ep-90, 0x1.4f1f52p-86 },
+ { 0x1.9b25dcp-91, 0x1.f08156p-87 },
+ { 0x1.2feeeep-91, 0x1.6f9f62p-87 },
+ { 0x1.c122bcp-92, 0x1.100ffap-87 },
+ { 0x1.4bb154p-92, 0x1.927ce6p-88 },
+ { 0x1.e9ae56p-93, 0x1.2992f4p-88 },
+ { 0x1.6948e8p-93, 0x1.b7cccap-89 },
+ { 0x1.0a6cd2p-93, 0x1.44d7c4p-89 },
+ { 0x1.88c0cap-94, 0x1.dfa22p-90 },
+ { 0x1.215988p-94, 0x1.61eb26p-90 },
+ { 0x1.aa222ap-95, 0x1.0506e2p-90 },
+ { 0x1.39a30ep-95, 0x1.80d828p-91 },
+ { 0x1.cd740ep-96, 0x1.1b8f04p-91 },
+ { 0x1.534d82p-96, 0x1.a1a7ecp-92 },
+ { 0x1.f2bb06p-97, 0x1.336f3p-92 },
+ { 0x1.6e5b34p-97, 0x1.c46172p-93 },
+ { 0x1.0cfc82p-97, 0x1.4cab82p-93 },
+ { 0x1.8acc82p-98, 0x1.e9094cp-94 },
+ { 0x1.219686p-98, 0x1.67465p-94 },
+ { 0x1.a89fa6p-99, 0x1.07d0b8p-94 },
+ { 0x1.372982p-99, 0x1.833ffap-95 },
+ { 0x1.c7d094p-100, 0x1.1c147ap-95 },
+ { 0x1.4db1c8p-100, 0x1.a096ccp-96 },
+ { 0x1.e858d8p-101, 0x1.314decp-96 },
+ { 0x1.6529ep-101, 0x1.bf46cep-97 },
+ { 0x1.0517bap-101, 0x1.47796ap-97 },
+ { 0x1.7d8a8p-102, 0x1.df49a2p-98 },
+ { 0x1.16a46p-102, 0x1.5e9198p-98 },
+ { 0x1.96ca76p-103, 0x1.004b34p-98 },
+ { 0x1.28cb2cp-103, 0x1.768f3ep-99 },
+ { 0x1.b0de98p-104, 0x1.1190d2p-99 },
+ },
+ };
diff --git a/sysdeps/aarch64/fpu/erfcf_sve.c b/sysdeps/aarch64/fpu/erfcf_sve.c
new file mode 100644
index 0000000000..48d1677eb4
--- /dev/null
+++ b/sysdeps/aarch64/fpu/erfcf_sve.c
@@ -0,0 +1,113 @@
+/* Single-precision vector (SVE) erfc function
+
+ Copyright (C) 2024 Free Software Foundation, Inc.
+ This file is part of the GNU C Library.
+
+ The GNU C Library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ The GNU C Library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with the GNU C Library; if not, see
+ <https://www.gnu.org/licenses/>. */
+
+#include "sv_math.h"
+
+static const struct data
+{
+ uint32_t off_idx, off_arr;
+ float max, shift;
+ float third, two_thirds, two_over_fifteen, two_over_five, tenth;
+} data = {
+ /* Set an offset so the range of the index used for lookup is 644, and it can
+ be clamped using a saturated add. */
+ .off_idx = 0xb7fffd7b, /* 0xffffffff - asuint(shift) - 644. */
+ .off_arr = 0xfffffd7b, /* 0xffffffff - 644. */
+ .max = 10.0625f, /* 644/64. */
+ .shift = 0x1p17f,
+ .third = 0x1.555556p-2f,
+ .two_thirds = 0x1.555556p-1f,
+ .two_over_fifteen = 0x1.111112p-3f,
+ .two_over_five = -0x1.99999ap-2f,
+ .tenth = -0x1.99999ap-4f,
+};
+
+#define SignMask 0x80000000
+#define TableScale 0x28000000 /* 0x1p-47. */
+
+/* Optimized single-precision vector erfcf(x).
+ Approximation based on series expansion near x rounded to
+ nearest multiple of 1/64.
+ Let d = x - r, and scale = 2 / sqrt(pi) * exp(-r^2). For x near r,
+
+ erfc(x) ~ erfc(r) - scale * d * poly(r, d), with
+
+ poly(r, d) = 1 - r d + (2/3 r^2 - 1/3) d^2 - r (1/3 r^2 - 1/2) d^3
+ + (2/15 r^4 - 2/5 r^2 + 1/10) d^4
+
+ Values of erfc(r) and scale are read from lookup tables. Stored values
+ are scaled to avoid hitting the subnormal range.
+
+ Note that for x < 0, erfc(x) = 2.0 - erfc(-x).
+
+ Maximum error: 1.63 ULP (~1.0 ULP for x < 0.0).
+ _ZGVsMxv_erfcf(0x1.1dbf7ap+3) got 0x1.f51212p-120
+ want 0x1.f51216p-120. */
+svfloat32_t SV_NAME_F1 (erfc) (svfloat32_t x, const svbool_t pg)
+{
+ const struct data *dat = ptr_barrier (&data);
+
+ svfloat32_t a = svabs_x (pg, x);
+
+ /* Clamp input at |x| <= 10.0 + 4/64. */
+ a = svmin_x (pg, a, dat->max);
+
+ /* Reduce x to the nearest multiple of 1/64. */
+ svfloat32_t shift = sv_f32 (dat->shift);
+ svfloat32_t z = svadd_x (pg, a, shift);
+
+ /* Saturate index for the NaN case. */
+ svuint32_t i = svqadd (svreinterpret_u32 (z), dat->off_idx);
+
+ /* Lookup erfc(r) and 2/sqrt(pi)*exp(-r^2) in tables. */
+ i = svmul_x (pg, i, 2);
+ const float32_t *p = &__erfcf_data.tab[0].erfc - 2 * dat->off_arr;
+ svfloat32_t erfcr = svld1_gather_index (pg, p, i);
+ svfloat32_t scale = svld1_gather_index (pg, p + 1, i);
+
+ /* erfc(x) ~ erfc(r) - scale * d * poly(r, d). */
+ svfloat32_t r = svsub_x (pg, z, shift);
+ svfloat32_t d = svsub_x (pg, a, r);
+ svfloat32_t d2 = svmul_x (pg, d, d);
+ svfloat32_t r2 = svmul_x (pg, r, r);
+
+ svfloat32_t coeffs = svld1rq (svptrue_b32 (), &dat->third);
+ svfloat32_t third = svdup_lane (coeffs, 0);
+
+ svfloat32_t p1 = r;
+ svfloat32_t p2 = svmls_lane (third, r2, coeffs, 1);
+ svfloat32_t p3 = svmul_x (pg, r, svmla_lane (sv_f32 (-0.5), r2, coeffs, 0));
+ svfloat32_t p4 = svmla_lane (sv_f32 (dat->two_over_five), r2, coeffs, 2);
+ p4 = svmls_x (pg, sv_f32 (dat->tenth), r2, p4);
+
+ svfloat32_t y = svmla_x (pg, p3, d, p4);
+ y = svmla_x (pg, p2, d, y);
+ y = svmla_x (pg, p1, d, y);
+
+ /* Solves the |x| = inf/nan case. */
+ y = svmls_x (pg, erfcr, scale, svmls_x (pg, d, d2, y));
+
+ /* Offset equals 2.0f if sign, else 0.0f. */
+ svuint32_t sign = svand_x (pg, svreinterpret_u32 (x), SignMask);
+ svfloat32_t off = svreinterpret_f32 (svlsr_x (pg, sign, 1));
+ /* Handle sign and scale back in a single fma. */
+ svfloat32_t fac = svreinterpret_f32 (svorr_x (pg, sign, TableScale));
+
+ return svmla_x (pg, off, fac, y);
+}
diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index 7aeda880bd..f2d8714075 100644
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -33,6 +33,7 @@ VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
VPCS_VECTOR_WRAPPER (cosh_advsimd, _ZGVnN2v_cosh)
VPCS_VECTOR_WRAPPER (erf_advsimd, _ZGVnN2v_erf)
+VPCS_VECTOR_WRAPPER (erfc_advsimd, _ZGVnN2v_erfc)
VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp)
VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10)
VPCS_VECTOR_WRAPPER (exp2_advsimd, _ZGVnN2v_exp2)
diff --git a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
index 95f1ec5222..37873d5e43 100644
--- a/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-sve-wrappers.c
@@ -52,6 +52,7 @@ SVE_VECTOR_WRAPPER_ff (atan2_sve, _ZGVsMxvv_atan2)
SVE_VECTOR_WRAPPER (cos_sve, _ZGVsMxv_cos)
SVE_VECTOR_WRAPPER (cosh_sve, _ZGVsMxv_cosh)
SVE_VECTOR_WRAPPER (erf_sve, _ZGVsMxv_erf)
+SVE_VECTOR_WRAPPER (erfc_sve, _ZGVsMxv_erfc)
SVE_VECTOR_WRAPPER (exp_sve, _ZGVsMxv_exp)
SVE_VECTOR_WRAPPER (exp10_sve, _ZGVsMxv_exp10)
SVE_VECTOR_WRAPPER (exp2_sve, _ZGVsMxv_exp2)
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
index bd6800e91c..08e33115b9 100644
--- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c
@@ -33,6 +33,7 @@ VPCS_VECTOR_WRAPPER_ff (atan2f_advsimd, _ZGVnN4vv_atan2f)
VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf)
VPCS_VECTOR_WRAPPER (coshf_advsimd, _ZGVnN4v_coshf)
VPCS_VECTOR_WRAPPER (erff_advsimd, _ZGVnN4v_erff)
+VPCS_VECTOR_WRAPPER (erfcf_advsimd, _ZGVnN4v_erfcf)
VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf)
VPCS_VECTOR_WRAPPER (exp10f_advsimd, _ZGVnN4v_exp10f)
VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f)
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
index 35ca305fdd..025daa662e 100644
--- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c
@@ -52,6 +52,7 @@ SVE_VECTOR_WRAPPER_ff (atan2f_sve, _ZGVsMxvv_atan2f)
SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf)
SVE_VECTOR_WRAPPER (coshf_sve, _ZGVsMxv_coshf)
SVE_VECTOR_WRAPPER (erff_sve, _ZGVsMxv_erff)
+SVE_VECTOR_WRAPPER (erfcf_sve, _ZGVsMxv_erfcf)
SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf)
SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f)
SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f)
diff --git a/sysdeps/aarch64/fpu/vecmath_config.h b/sysdeps/aarch64/fpu/vecmath_config.h
index 3f0b5f4764..c8cfc03bc0 100644
--- a/sysdeps/aarch64/fpu/vecmath_config.h
+++ b/sysdeps/aarch64/fpu/vecmath_config.h
@@ -114,4 +114,20 @@ extern const struct sv_erf_data
double scale[769];
} __sv_erf_data attribute_hidden;
+extern const struct erfc_data
+{
+ struct
+ {
+ double erfc, scale;
+ } tab[3488];
+} __erfc_data attribute_hidden;
+
+extern const struct erfcf_data
+{
+ struct
+ {
+ float erfc, scale;
+ } tab[645];
+} __erfcf_data attribute_hidden;
+
#endif
diff --git a/sysdeps/aarch64/libm-test-ulps b/sysdeps/aarch64/libm-test-ulps
index c26d39e644..116a5404f5 100644
--- a/sysdeps/aarch64/libm-test-ulps
+++ b/sysdeps/aarch64/libm-test-ulps
@@ -1017,11 +1017,19 @@ double: 2
float: 2
ldouble: 4
+Function: "erfc_advsimd":
+double: 1
+float: 1
+
Function: "erfc_downward":
double: 4
float: 4
ldouble: 5
+Function: "erfc_sve":
+double: 1
+float: 1
+
Function: "erfc_towardzero":
double: 3
float: 3
diff --git a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
index 396082f6a7..26c3fbf18b 100644
--- a/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
+++ b/sysdeps/unix/sysv/linux/aarch64/libmvec.abilist
@@ -82,6 +82,8 @@ GLIBC_2.40 _ZGVnN2v_atanhf F
GLIBC_2.40 _ZGVnN2v_cosh F
GLIBC_2.40 _ZGVnN2v_coshf F
GLIBC_2.40 _ZGVnN2v_erf F
+GLIBC_2.40 _ZGVnN2v_erfc F
+GLIBC_2.40 _ZGVnN2v_erfcf F
GLIBC_2.40 _ZGVnN2v_erff F
GLIBC_2.40 _ZGVnN2v_sinh F
GLIBC_2.40 _ZGVnN2v_sinhf F
@@ -91,6 +93,7 @@ GLIBC_2.40 _ZGVnN4v_acoshf F
GLIBC_2.40 _ZGVnN4v_asinhf F
GLIBC_2.40 _ZGVnN4v_atanhf F
GLIBC_2.40 _ZGVnN4v_coshf F
+GLIBC_2.40 _ZGVnN4v_erfcf F
GLIBC_2.40 _ZGVnN4v_erff F
GLIBC_2.40 _ZGVnN4v_sinhf F
GLIBC_2.40 _ZGVnN4v_tanhf F
@@ -103,6 +106,8 @@ GLIBC_2.40 _ZGVsMxv_atanhf F
GLIBC_2.40 _ZGVsMxv_cosh F
GLIBC_2.40 _ZGVsMxv_coshf F
GLIBC_2.40 _ZGVsMxv_erf F
+GLIBC_2.40 _ZGVsMxv_erfc F
+GLIBC_2.40 _ZGVsMxv_erfcf F
GLIBC_2.40 _ZGVsMxv_erff F
GLIBC_2.40 _ZGVsMxv_sinh F
GLIBC_2.40 _ZGVsMxv_sinhf F
--
2.27.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/8] aarch64/fpu: Add vector variants of erf
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
` (6 preceding siblings ...)
2024-02-20 16:59 ` [PATCH 8/8] aarch64/fpu: Add vector variants of erfc Joe Ramsay
@ 2024-03-21 14:37 ` Szabolcs Nagy
7 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:37 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 7 +-
> sysdeps/aarch64/fpu/Versions | 7 +
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
> sysdeps/aarch64/fpu/erf_advsimd.c | 161 ++
> sysdeps/aarch64/fpu/erf_data.c | 800 +++++++++
> sysdeps/aarch64/fpu/erf_sve.c | 115 ++
> sysdeps/aarch64/fpu/erff_advsimd.c | 123 ++
> sysdeps/aarch64/fpu/erff_data.c | 544 ++++++
> sysdeps/aarch64/fpu/erff_sve.c | 93 +
> sysdeps/aarch64/fpu/sv_erf_data.c | 1570 +++++++++++++++++
> sysdeps/aarch64/fpu/sv_erff_data.c | 1058 +++++++++++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/fpu/vecmath_config.h | 28 +
> sysdeps/aarch64/libm-test-ulps | 8 +
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 19 files changed, 4531 insertions(+), 1 deletion(-)
> create mode 100644 sysdeps/aarch64/fpu/erf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/erf_data.c
> create mode 100644 sysdeps/aarch64/fpu/erf_sve.c
> create mode 100644 sysdeps/aarch64/fpu/erff_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/erff_data.c
> create mode 100644 sysdeps/aarch64/fpu/erff_sve.c
> create mode 100644 sysdeps/aarch64/fpu/sv_erf_data.c
> create mode 100644 sysdeps/aarch64/fpu/sv_erff_data.c
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/8] aarch64/fpu: Add vector variants of cosh
2024-02-20 16:59 ` [PATCH 2/8] aarch64/fpu: Add vector variants of cosh Joe Ramsay
@ 2024-03-21 14:38 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:38 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 4 +-
> sysdeps/aarch64/fpu/Versions | 5 +
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
> sysdeps/aarch64/fpu/cosh_advsimd.c | 108 +++++++++++++++++
> sysdeps/aarch64/fpu/cosh_sve.c | 105 +++++++++++++++++
> sysdeps/aarch64/fpu/coshf_advsimd.c | 84 +++++++++++++
> sysdeps/aarch64/fpu/coshf_sve.c | 59 ++++++++++
> sysdeps/aarch64/fpu/sv_expf_inline.h | 75 ++++++++++++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/fpu/v_exp_tail_data.c | 110 ++++++++++++++++++
> sysdeps/aarch64/fpu/v_expf_inline.h | 71 +++++++++++
> sysdeps/aarch64/fpu/vecmath_config.h | 2 +
> sysdeps/aarch64/libm-test-ulps | 8 ++
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 18 files changed, 648 insertions(+), 1 deletion(-)
> create mode 100644 sysdeps/aarch64/fpu/cosh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/cosh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/coshf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/coshf_sve.c
> create mode 100644 sysdeps/aarch64/fpu/sv_expf_inline.h
> create mode 100644 sysdeps/aarch64/fpu/v_exp_tail_data.c
> create mode 100644 sysdeps/aarch64/fpu/v_expf_inline.h
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/8] aarch64/fpu: Add vector variants of acosh
2024-02-20 16:59 ` [PATCH 3/8] aarch64/fpu: Add vector variants of acosh Joe Ramsay
@ 2024-03-21 14:42 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:42 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 1 +
> sysdeps/aarch64/fpu/Versions | 5 +
> sysdeps/aarch64/fpu/acosh_advsimd.c | 67 +++++++++++
> sysdeps/aarch64/fpu/acosh_sve.c | 51 ++++++++
> sysdeps/aarch64/fpu/acoshf_advsimd.c | 78 +++++++++++++
> sysdeps/aarch64/fpu/acoshf_sve.c | 49 ++++++++
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
> sysdeps/aarch64/fpu/sv_log1p_inline.h | 109 ++++++++++++++++++
> sysdeps/aarch64/fpu/sv_log1pf_inline.h | 76 ++++++++++++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/fpu/v_log1p_inline.h | 103 +++++++++++++++++
> sysdeps/aarch64/fpu/v_log1pf_inline.h | 78 +++++++++++++
> sysdeps/aarch64/fpu/v_math.h | 10 ++
> sysdeps/aarch64/libm-test-ulps | 8 ++
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 19 files changed, 653 insertions(+)
> create mode 100644 sysdeps/aarch64/fpu/acosh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/acosh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/acoshf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/acoshf_sve.c
> create mode 100644 sysdeps/aarch64/fpu/sv_log1p_inline.h
> create mode 100644 sysdeps/aarch64/fpu/sv_log1pf_inline.h
> create mode 100644 sysdeps/aarch64/fpu/v_log1p_inline.h
> create mode 100644 sysdeps/aarch64/fpu/v_log1pf_inline.h
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/8] aarch64/fpu: Add vector variants of asinh
2024-02-20 16:59 ` [PATCH 4/8] aarch64/fpu: Add vector variants of asinh Joe Ramsay
@ 2024-03-21 14:44 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:44 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 1 +
> sysdeps/aarch64/fpu/Versions | 5 +
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/asinh_advsimd.c | 171 ++++++++++++++++++
> sysdeps/aarch64/fpu/asinh_sve.c | 150 +++++++++++++++
> sysdeps/aarch64/fpu/asinhf_advsimd.c | 80 ++++++++
> sysdeps/aarch64/fpu/asinhf_sve.c | 56 ++++++
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/libm-test-ulps | 8 +
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 14 files changed, 489 insertions(+)
> create mode 100644 sysdeps/aarch64/fpu/asinh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/asinh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/asinhf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/asinhf_sve.c
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 5/8] aarch64/fpu: Add vector variants of atanh
2024-02-20 16:59 ` [PATCH 5/8] aarch64/fpu: Add vector variants of atanh Joe Ramsay
@ 2024-03-21 14:45 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:45 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 1 +
> sysdeps/aarch64/fpu/Versions | 5 ++
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/atanh_advsimd.c | 64 +++++++++++++++
> sysdeps/aarch64/fpu/atanh_sve.c | 59 ++++++++++++++
> sysdeps/aarch64/fpu/atanhf_advsimd.c | 79 +++++++++++++++++++
> sysdeps/aarch64/fpu/atanhf_sve.c | 54 +++++++++++++
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/libm-test-ulps | 8 ++
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 ++
> 14 files changed, 288 insertions(+)
> create mode 100644 sysdeps/aarch64/fpu/atanh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/atanh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/atanhf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/atanhf_sve.c
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 6/8] aarch64/fpu: Add vector variants of sinh
2024-02-20 16:59 ` [PATCH 6/8] aarch64/fpu: Add vector variants of sinh Joe Ramsay
@ 2024-03-21 14:46 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:46 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK with one nit below.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 1 +
> sysdeps/aarch64/fpu/Versions | 15 ++-
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
> sysdeps/aarch64/fpu/sinh_advsimd.c | 121 ++++++++++++++++++
> sysdeps/aarch64/fpu/sinh_sve.c | 107 ++++++++++++++++
> sysdeps/aarch64/fpu/sinhf_advsimd.c | 88 +++++++++++++
> sysdeps/aarch64/fpu/sinhf_sve.c | 67 ++++++++++
> sysdeps/aarch64/fpu/sv_expm1f_inline.h | 84 ++++++++++++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/fpu/v_expm1f_inline.h | 73 +++++++++++
> sysdeps/aarch64/libm-test-ulps | 8 ++
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 16 files changed, 577 insertions(+), 5 deletions(-)
> create mode 100644 sysdeps/aarch64/fpu/sinh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/sinh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/sinhf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/sinhf_sve.c
> create mode 100644 sysdeps/aarch64/fpu/sv_expm1f_inline.h
> create mode 100644 sysdeps/aarch64/fpu/v_expm1f_inline.h
...
> diff --git a/sysdeps/aarch64/fpu/Versions b/sysdeps/aarch64/fpu/Versions
> index 86c08c1fa3..4774b3efea 100644
> --- a/sysdeps/aarch64/fpu/Versions
> +++ b/sysdeps/aarch64/fpu/Versions
> @@ -89,6 +89,11 @@ libmvec {
> _ZGVnN4v_asinhf;
> _ZGVsMxv_asinh;
> _ZGVsMxv_asinhf;
> + _ZGVnN2v_atanh;
> + _ZGVnN2v_atanhf;
> + _ZGVnN4v_atanhf;
> + _ZGVsMxv_atanh;
> + _ZGVsMxv_atanhf;
> _ZGVnN2v_cosh;
> _ZGVnN2v_coshf;
> _ZGVnN4v_coshf;
> @@ -99,10 +104,10 @@ libmvec {
> _ZGVnN4v_erff;
> _ZGVsMxv_erf;
> _ZGVsMxv_erff;
> - _ZGVnN2v_atanh;
> - _ZGVnN2v_atanhf;
> - _ZGVnN4v_atanhf;
> - _ZGVsMxv_atanh;
> - _ZGVsMxv_atanhf;
this should be in the previous patch.
> + _ZGVnN2v_sinh;
> + _ZGVnN2v_sinhf;
> + _ZGVnN4v_sinhf;
> + _ZGVsMxv_sinh;
> + _ZGVsMxv_sinhf;
> }
> }
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 7/8] aarch64/fpu: Add vector variants of tanh
2024-02-20 16:59 ` [PATCH 7/8] aarch64/fpu: Add vector variants of tanh Joe Ramsay
@ 2024-03-21 14:51 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:51 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK. (non-aarch64 changes look OK too)
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> math/auto-libm-test-in | 2 +-
> math/auto-libm-test-out-tanh | 50 ++++----
> sysdeps/aarch64/fpu/Makefile | 3 +-
> sysdeps/aarch64/fpu/Versions | 5 +
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 ++
> sysdeps/aarch64/fpu/tanh_advsimd.c | 109 ++++++++++++++++++
> sysdeps/aarch64/fpu/tanh_sve.c | 100 ++++++++++++++++
> sysdeps/aarch64/fpu/tanhf_advsimd.c | 76 ++++++++++++
> sysdeps/aarch64/fpu/tanhf_sve.c | 61 ++++++++++
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/libm-test-ulps | 8 ++
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 16 files changed, 405 insertions(+), 27 deletions(-)
> create mode 100644 sysdeps/aarch64/fpu/tanh_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/tanh_sve.c
> create mode 100644 sysdeps/aarch64/fpu/tanhf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/tanhf_sve.c
>
> diff --git a/math/auto-libm-test-in b/math/auto-libm-test-in
> index d728f97770..05d7ae5002 100644
> --- a/math/auto-libm-test-in
> +++ b/math/auto-libm-test-in
> @@ -7747,7 +7747,7 @@ tan min_subnorm
> tan -min_subnorm
>
> tanh 0
> -tanh -0
> +tanh -0 no-mathvec
> tanh 0.75
> tanh -0.75
> tanh 1.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 8/8] aarch64/fpu: Add vector variants of erfc
2024-02-20 16:59 ` [PATCH 8/8] aarch64/fpu: Add vector variants of erfc Joe Ramsay
@ 2024-03-21 14:52 ` Szabolcs Nagy
0 siblings, 0 replies; 16+ messages in thread
From: Szabolcs Nagy @ 2024-03-21 14:52 UTC (permalink / raw)
To: Joe Ramsay, libc-alpha
The 02/20/2024 16:59, Joe Ramsay wrote:
> ---
OK.
Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
> Thanks,
> Joe
> sysdeps/aarch64/fpu/Makefile | 5 +-
> sysdeps/aarch64/fpu/Versions | 5 +
> sysdeps/aarch64/fpu/advsimd_f32_protos.h | 1 +
> sysdeps/aarch64/fpu/bits/math-vector.h | 8 +
> sysdeps/aarch64/fpu/erfc_advsimd.c | 201 +
> sysdeps/aarch64/fpu/erfc_data.c | 3519 +++++++++++++++++
> sysdeps/aarch64/fpu/erfc_sve.c | 167 +
> sysdeps/aarch64/fpu/erfcf_advsimd.c | 170 +
> sysdeps/aarch64/fpu/erfcf_data.c | 676 ++++
> sysdeps/aarch64/fpu/erfcf_sve.c | 113 +
> .../fpu/test-double-advsimd-wrappers.c | 1 +
> .../aarch64/fpu/test-double-sve-wrappers.c | 1 +
> .../aarch64/fpu/test-float-advsimd-wrappers.c | 1 +
> sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 +
> sysdeps/aarch64/fpu/vecmath_config.h | 16 +
> sysdeps/aarch64/libm-test-ulps | 8 +
> .../unix/sysv/linux/aarch64/libmvec.abilist | 5 +
> 17 files changed, 4897 insertions(+), 1 deletion(-)
> create mode 100644 sysdeps/aarch64/fpu/erfc_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/erfc_data.c
> create mode 100644 sysdeps/aarch64/fpu/erfc_sve.c
> create mode 100644 sysdeps/aarch64/fpu/erfcf_advsimd.c
> create mode 100644 sysdeps/aarch64/fpu/erfcf_data.c
> create mode 100644 sysdeps/aarch64/fpu/erfcf_sve.c
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-03-21 14:53 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-20 16:59 [PATCH 1/8] aarch64/fpu: Add vector variants of erf Joe Ramsay
2024-02-20 16:59 ` [PATCH 2/8] aarch64/fpu: Add vector variants of cosh Joe Ramsay
2024-03-21 14:38 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 3/8] aarch64/fpu: Add vector variants of acosh Joe Ramsay
2024-03-21 14:42 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 4/8] aarch64/fpu: Add vector variants of asinh Joe Ramsay
2024-03-21 14:44 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 5/8] aarch64/fpu: Add vector variants of atanh Joe Ramsay
2024-03-21 14:45 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 6/8] aarch64/fpu: Add vector variants of sinh Joe Ramsay
2024-03-21 14:46 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 7/8] aarch64/fpu: Add vector variants of tanh Joe Ramsay
2024-03-21 14:51 ` Szabolcs Nagy
2024-02-20 16:59 ` [PATCH 8/8] aarch64/fpu: Add vector variants of erfc Joe Ramsay
2024-03-21 14:52 ` Szabolcs Nagy
2024-03-21 14:37 ` [PATCH 1/8] aarch64/fpu: Add vector variants of erf Szabolcs Nagy
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