From: Naohiro Tamura <naohirot@fujitsu.com>
To: libc-alpha@sourceware.org
Cc: Naohiro Tamura <naohirot@jp.fujitsu.com>
Subject: [PATCH v2 1/6] config: Added HAVE_AARCH64_SVE_ASM for aarch64
Date: Wed, 12 May 2021 09:26:40 +0000 [thread overview]
Message-ID: <20210512092640.901076-1-naohirot@fujitsu.com> (raw)
In-Reply-To: <20210512092308.900998-1-naohirot@fujitsu.com>
From: Naohiro Tamura <naohirot@jp.fujitsu.com>
This patch checks if assembler supports '-march=armv8.2-a+sve' to
generate SVE code or not, and then define HAVE_AARCH64_SVE_ASM macro.
---
config.h.in | 5 +++++
sysdeps/aarch64/configure | 28 ++++++++++++++++++++++++++++
sysdeps/aarch64/configure.ac | 15 +++++++++++++++
3 files changed, 48 insertions(+)
diff --git a/config.h.in b/config.h.in
index 99036b887f..13fba9bb8d 100644
--- a/config.h.in
+++ b/config.h.in
@@ -121,6 +121,11 @@
/* AArch64 PAC-RET code generation is enabled. */
#define HAVE_AARCH64_PAC_RET 0
+/* Assembler support ARMv8.2-A SVE.
+ This macro becomes obsolete when glibc increased the minimum
+ required version of GNU 'binutils' to 2.28 or later. */
+#define HAVE_AARCH64_SVE_ASM 0
+
/* ARC big endian ABI */
#undef HAVE_ARC_BE
diff --git a/sysdeps/aarch64/configure b/sysdeps/aarch64/configure
index 83c3a23e44..4c1fac49f3 100644
--- a/sysdeps/aarch64/configure
+++ b/sysdeps/aarch64/configure
@@ -304,3 +304,31 @@ fi
$as_echo "$libc_cv_aarch64_variant_pcs" >&6; }
config_vars="$config_vars
aarch64-variant-pcs = $libc_cv_aarch64_variant_pcs"
+
+# Check if asm support armv8.2-a+sve
+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for SVE support in assembler" >&5
+$as_echo_n "checking for SVE support in assembler... " >&6; }
+if ${libc_cv_asm_sve+:} false; then :
+ $as_echo_n "(cached) " >&6
+else
+ cat > conftest.s <<\EOF
+ ptrue p0.b
+EOF
+if { ac_try='${CC-cc} -c -march=armv8.2-a+sve conftest.s 1>&5'
+ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
+ (eval $ac_try) 2>&5
+ ac_status=$?
+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
+ test $ac_status = 0; }; }; then
+ libc_cv_aarch64_sve_asm=yes
+else
+ libc_cv_aarch64_sve_asm=no
+fi
+rm -f conftest*
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libc_cv_asm_sve" >&5
+$as_echo "$libc_cv_asm_sve" >&6; }
+if test $libc_cv_aarch64_sve_asm = yes; then
+ $as_echo "#define HAVE_AARCH64_SVE_ASM 1" >>confdefs.h
+
+fi
diff --git a/sysdeps/aarch64/configure.ac b/sysdeps/aarch64/configure.ac
index 66f755078a..3347c13fa1 100644
--- a/sysdeps/aarch64/configure.ac
+++ b/sysdeps/aarch64/configure.ac
@@ -90,3 +90,18 @@ EOF
fi
rm -rf conftest.*])
LIBC_CONFIG_VAR([aarch64-variant-pcs], [$libc_cv_aarch64_variant_pcs])
+
+# Check if asm support armv8.2-a+sve
+AC_CACHE_CHECK(for SVE support in assembler, libc_cv_asm_sve, [dnl
+cat > conftest.s <<\EOF
+ ptrue p0.b
+EOF
+if AC_TRY_COMMAND(${CC-cc} -c -march=armv8.2-a+sve conftest.s 1>&AS_MESSAGE_LOG_FD); then
+ libc_cv_aarch64_sve_asm=yes
+else
+ libc_cv_aarch64_sve_asm=no
+fi
+rm -f conftest*])
+if test $libc_cv_aarch64_sve_asm = yes; then
+ AC_DEFINE(HAVE_AARCH64_SVE_ASM)
+fi
--
2.17.1
next prev parent reply other threads:[~2021-05-12 9:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-17 2:28 [PATCH 0/5] Added optimized memcpy/memmove/memset for A64FX Naohiro Tamura
2021-03-17 2:33 ` [PATCH 1/5] config: Added HAVE_SVE_ASM_SUPPORT for aarch64 Naohiro Tamura
2021-03-29 12:11 ` Szabolcs Nagy via Libc-alpha
2021-03-30 6:19 ` naohirot
2021-03-17 2:34 ` [PATCH 2/5] aarch64: Added optimized memcpy and memmove for A64FX Naohiro Tamura
2021-03-29 12:44 ` Szabolcs Nagy via Libc-alpha
2021-03-30 7:17 ` naohirot
2021-03-17 2:34 ` [PATCH 3/5] aarch64: Added optimized memset " Naohiro Tamura
2021-03-17 2:35 ` [PATCH 4/5] scripts: Added Vector Length Set test helper script Naohiro Tamura
2021-03-29 13:20 ` Szabolcs Nagy via Libc-alpha
2021-03-30 7:25 ` naohirot
2021-03-17 2:35 ` [PATCH 5/5] benchtests: Added generic_memcpy and generic_memmove to large benchtests Naohiro Tamura
2021-03-29 12:03 ` [PATCH 0/5] Added optimized memcpy/memmove/memset for A64FX Szabolcs Nagy via Libc-alpha
2021-05-10 1:45 ` naohirot
2021-05-14 13:35 ` Szabolcs Nagy via Libc-alpha
2021-05-19 0:11 ` naohirot
2021-05-12 9:23 ` [PATCH v2 0/6] aarch64: " Naohiro Tamura
2021-05-12 9:26 ` Naohiro Tamura [this message]
2021-05-26 10:05 ` [PATCH v2 1/6] config: Added HAVE_AARCH64_SVE_ASM for aarch64 Szabolcs Nagy via Libc-alpha
2021-05-12 9:27 ` [PATCH v2 2/6] aarch64: define BTI_C and BTI_J macros as NOP unless HAVE_AARCH64_BTI Naohiro Tamura
2021-05-26 10:06 ` Szabolcs Nagy via Libc-alpha
2021-05-12 9:28 ` [PATCH v2 3/6] aarch64: Added optimized memcpy and memmove for A64FX Naohiro Tamura
2021-05-26 10:19 ` Szabolcs Nagy via Libc-alpha
2021-05-12 9:28 ` [PATCH v2 4/6] aarch64: Added optimized memset " Naohiro Tamura
2021-05-26 10:22 ` Szabolcs Nagy via Libc-alpha
2021-05-12 9:29 ` [PATCH v2 5/6] scripts: Added Vector Length Set test helper script Naohiro Tamura
2021-05-12 16:58 ` Joseph Myers
2021-05-13 9:53 ` naohirot
2021-05-20 7:34 ` Naohiro Tamura
2021-05-26 10:24 ` Szabolcs Nagy via Libc-alpha
2021-05-12 9:29 ` [PATCH v2 6/6] benchtests: Fixed bench-memcpy-random: buf1: mprotect failed Naohiro Tamura
2021-05-26 10:25 ` Szabolcs Nagy via Libc-alpha
2021-05-27 0:22 ` [PATCH v2 0/6] aarch64: Added optimized memcpy/memmove/memset for A64FX naohirot
2021-05-27 23:50 ` naohirot
2021-05-27 7:42 ` [PATCH v3 1/2] aarch64: Added optimized memcpy and memmove " Naohiro Tamura
2021-05-27 7:44 ` [PATCH v3 2/2] aarch64: Added optimized memset " Naohiro Tamura
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