From: Wilco Dijkstra via Libc-alpha <libc-alpha@sourceware.org>
To: "naohirot@fujitsu.com" <naohirot@fujitsu.com>
Cc: 'GNU C Library' <libc-alpha@sourceware.org>
Subject: Re: [PATCH v3 2/5] AArch64: Improve A64FX memset
Date: Mon, 9 Aug 2021 16:16:29 +0000 [thread overview]
Message-ID: <VE1PR08MB55990565C910027EDDC9DB2D83F69@VE1PR08MB5599.eurprd08.prod.outlook.com> (raw)
In-Reply-To: <TYAPR01MB602588CAC2CC4A22BD782BFDDFF09@TYAPR01MB6025.jpnprd01.prod.outlook.com>
Hi Naohiro,
> > + // align dst to CACHE_LINE_SIZE byte boundary
> > + and tmp2, dst, CACHE_LINE_SIZE - 1
> > + sub tmp2, tmp2, CACHE_LINE_SIZE
> "tmp2" becomes always minus value.
> I felt that it would be easier to understand and natural if it is reversed like this:
>
> sub tmp2, CACHE_LINE_SIZE, tmp2
That's not a valid instruction though. I've just removed it in v4 since we can
delay the cacheline adjustment to dst and count to later instructions.
> But comparing nonzero fill graph[6] with zero fill graph[4],
> why DC ZVA is only effective more than 8MB for __memset_a64fx in spite
> that DC ZVA is effective from smaller size for __memset_generic?
Well it seems on A64FX DC ZVA is faster only when data is not in L1. So it may
be feasible to use DC ZVA for smaller sizes.
Cheers,
Wilco
prev parent reply other threads:[~2021-08-09 16:17 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-22 16:00 [PATCH v3 2/5] AArch64: Improve A64FX memset Wilco Dijkstra via Libc-alpha
2021-08-02 13:29 ` naohirot--- via Libc-alpha
2021-08-03 3:08 ` naohirot--- via Libc-alpha
2021-08-03 5:03 ` naohirot--- via Libc-alpha
2021-08-09 16:16 ` Wilco Dijkstra via Libc-alpha [this message]
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