* [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332)
@ 2020-08-03 8:51 Florian Weimer via Libc-alpha
2020-08-03 16:05 ` Carlos O'Donell via Libc-alpha
0 siblings, 1 reply; 3+ messages in thread
From: Florian Weimer via Libc-alpha @ 2020-08-03 8:51 UTC (permalink / raw)
To: libc-alpha; +Cc: Tulio Magno Quites Machado Filho
__GLRO loaded the word after the requested variable on big-endian
PowerPC, where LOWORD is 4. This can cause the memset implement
go wrong because the masking with the cache line size produces
wrong results, particularly if the loaded value happens to be 1.
The __GLRO macro is not used in any place where loading the lower
32-bit word of a 64-bit value is desired, so the +4 offset is always
wrong.
Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc
("powerpc: Move cache line size to rtld_global_ro") and bug 26332.
---
sysdeps/powerpc/powerpc32/sysdep.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h
index 2ba009e919..829eec266a 100644
--- a/sysdeps/powerpc/powerpc32/sysdep.h
+++ b/sysdeps/powerpc/powerpc32/sysdep.h
@@ -179,8 +179,8 @@ GOT_LABEL: ; \
#else
/* Position-dependent code does not require access to the GOT. */
# define __GLRO(rOUT, rGOT, member, offset) \
- lis rOUT,(member+LOWORD)@ha; \
- lwz rOUT,(member+LOWORD)@l(rOUT)
+ lis rOUT,(member)@ha; \
+ lwz rOUT,(member)@l(rOUT)
#endif /* PIC */
#endif /* __ASSEMBLER__ */
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332)
2020-08-03 8:51 [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332) Florian Weimer via Libc-alpha
@ 2020-08-03 16:05 ` Carlos O'Donell via Libc-alpha
2020-08-03 16:07 ` Florian Weimer via Libc-alpha
0 siblings, 1 reply; 3+ messages in thread
From: Carlos O'Donell via Libc-alpha @ 2020-08-03 16:05 UTC (permalink / raw)
To: Florian Weimer, libc-alpha; +Cc: Tulio Magno Quites Machado Filho
On 8/3/20 4:51 AM, Florian Weimer wrote:
> __GLRO loaded the word after the requested variable on big-endian
> PowerPC, where LOWORD is 4. This can cause the memset implement
> go wrong because the masking with the cache line size produces
> wrong results, particularly if the loaded value happens to be 1.
>
> The __GLRO macro is not used in any place where loading the lower
> 32-bit word of a 64-bit value is desired, so the +4 offset is always
> wrong.
Agreed.
I reviewed sysdeps/powerpc/powerpc32/sysdep.h, and:
sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
sysdeps/powerpc/powerpc32/sysdep.h
sysdeps/powerpc/powerpc32/memset.S
sysdeps/powerpc/powerpc32/a2/memcpy.S
I see only 32-bit word accesses and so the +4 offset is wrong. This
was likely just a copy-and-paste that came from similar code which
accesses the 64-bit HWCAP/HWCAP2 e.g. uint64_t _dl_hwcap.
The 64-bit sysdeps/powerpc/powerpc64/sysdep.h is different and doesn't
have this problem for obvious reasons (it can load a 64-bit value).
> Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc
> ("powerpc: Move cache line size to rtld_global_ro") and bug 26332.
Reviewed-by: Carlos O'Donell <carlos@redhat.com>
> ---
> sysdeps/powerpc/powerpc32/sysdep.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/sysdeps/powerpc/powerpc32/sysdep.h b/sysdeps/powerpc/powerpc32/sysdep.h
> index 2ba009e919..829eec266a 100644
> --- a/sysdeps/powerpc/powerpc32/sysdep.h
> +++ b/sysdeps/powerpc/powerpc32/sysdep.h
> @@ -179,8 +179,8 @@ GOT_LABEL: ; \
> #else
> /* Position-dependent code does not require access to the GOT. */
> # define __GLRO(rOUT, rGOT, member, offset) \
> - lis rOUT,(member+LOWORD)@ha; \
> - lwz rOUT,(member+LOWORD)@l(rOUT)
> + lis rOUT,(member)@ha; \
> + lwz rOUT,(member)@l(rOUT)
OK.
> #endif /* PIC */
>
> #endif /* __ASSEMBLER__ */
>
--
Cheers,
Carlos.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332)
2020-08-03 16:05 ` Carlos O'Donell via Libc-alpha
@ 2020-08-03 16:07 ` Florian Weimer via Libc-alpha
0 siblings, 0 replies; 3+ messages in thread
From: Florian Weimer via Libc-alpha @ 2020-08-03 16:07 UTC (permalink / raw)
To: Carlos O'Donell; +Cc: Tulio Magno Quites Machado Filho, libc-alpha
* Carlos O'Donell:
> On 8/3/20 4:51 AM, Florian Weimer wrote:
>> __GLRO loaded the word after the requested variable on big-endian
>> PowerPC, where LOWORD is 4. This can cause the memset implement
>> go wrong because the masking with the cache line size produces
>> wrong results, particularly if the loaded value happens to be 1.
>>
>> The __GLRO macro is not used in any place where loading the lower
>> 32-bit word of a 64-bit value is desired, so the +4 offset is always
>> wrong.
>
> Agreed.
>
> I reviewed sysdeps/powerpc/powerpc32/sysdep.h, and:
> sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h
> sysdeps/powerpc/powerpc32/sysdep.h
> sysdeps/powerpc/powerpc32/memset.S
> sysdeps/powerpc/powerpc32/a2/memcpy.S
>
> I see only 32-bit word accesses and so the +4 offset is wrong. This
> was likely just a copy-and-paste that came from similar code which
> accesses the 64-bit HWCAP/HWCAP2 e.g. uint64_t _dl_hwcap.
>
> The 64-bit sysdeps/powerpc/powerpc64/sysdep.h is different and doesn't
> have this problem for obvious reasons (it can load a 64-bit value).
>
>> Fixes commit 18363b4f010da9ba459b13310b113ac0647c2fcc
>> ("powerpc: Move cache line size to rtld_global_ro") and bug 26332.
>
> Reviewed-by: Carlos O'Donell <carlos@redhat.com>
Pushed as 7650321ce037302bfc2f026aa19e0213b8d02fe6.
Thanks,
Florian
^ permalink raw reply [flat|nested] 3+ messages in thread
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2020-08-03 8:51 [PATCH] powerpc: Fix incorrect cache line size load in memset (bug 26332) Florian Weimer via Libc-alpha
2020-08-03 16:05 ` Carlos O'Donell via Libc-alpha
2020-08-03 16:07 ` Florian Weimer via Libc-alpha
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