From mboxrd@z Thu Jan 1 00:00:00 1970 Path: news.gmane.org!.POSTED!not-for-mail From: DJ Delorie Newsgroups: gmane.comp.lib.glibc.alpha Subject: Re: riscv: fmax/fmin sNaN fix Date: Tue, 20 Feb 2018 12:12:30 -0500 Message-ID: References: NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain X-Trace: blaine.gmane.org 1519146639 17524 195.159.176.226 (20 Feb 2018 17:10:39 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Tue, 20 Feb 2018 17:10:39 +0000 (UTC) Cc: libc-alpha@sourceware.org, nd@arm.com To: Szabolcs Nagy Original-X-From: libc-alpha-return-90415-glibc-alpha=m.gmane.org@sourceware.org Tue Feb 20 18:10:35 2018 Return-path: Envelope-to: glibc-alpha@blaine.gmane.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:in-reply-to:date:message-id :mime-version:content-type; q=dns; s=default; b=HtGpbg6iRWLHZdS2 VTgk6SkBpz3XN/0YtvmrskPM98NQhi/8EKbJw4i0zGYyJa+8U7MAawvlILLB0NA1 zruEnTIRaXjtVJo8FVZ/Nu1mU9fVrcP/jOeyE6FBlZYvQGm/6uhnpJxKSVk7IO9z SKrbfNNfOsJ1t0PNCf5P/SiAktQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:in-reply-to:date:message-id :mime-version:content-type; s=default; bh=AZOshEClf7DrT3EdsSOQUl i7a1M=; b=m24S6dJtNVTwPTRhPS/QQSreNR/vvxM4/mYSqDUkptNpvDC8ls9OWB PfXsU3hXhKfI6OHnWBzfidoQlzzTeeTwaVKDZ8ITPIjThYI6f2up02uCpmkBumwX Nvh9vFGRC+Agkx6WyyTC3GcDL8Kh/JJiyVoP+0sd+7d5m3RQdD6O0= Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Original-Sender: libc-alpha-owner@sourceware.org Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=documents X-HELO: mx1.redhat.com In-Reply-To: (message from Szabolcs Nagy on Tue, 20 Feb 2018 10:26:01 +0000) Xref: news.gmane.org gmane.comp.lib.glibc.alpha:82747 Archived-At: Received: from server1.sourceware.org ([209.132.180.131] helo=sourceware.org) by blaine.gmane.org with esmtp (Exim 4.84_2) (envelope-from ) id 1eoBR4-0004CJ-5f for glibc-alpha@blaine.gmane.org; Tue, 20 Feb 2018 18:10:34 +0100 Received: (qmail 54626 invoked by alias); 20 Feb 2018 17:12:36 -0000 Received: (qmail 54615 invoked by uid 89); 20 Feb 2018 17:12:36 -0000 Szabolcs Nagy writes: > On 20/02/18 02:57, DJ Delorie wrote: >> >> RISC-V's FPU follows the IEEE spec, not the POSIX spec. This patch > ^^^^^^^^^ > which one? > (the next ieee revision will have different min/max operations) The one that doesn't match POSIX :-) The RISC-V fpu does this: fmax (sNAN,4) -> 4 GLIBC expects this: fmax (sNAN,4) -> qNAN (hmm... maybe it follows posix, not ieee... whatever, it doesn't do what glibc expects) Note that the RISC-V ISA spec 2.2 documents the sNAN->qNAN behavior, there's a patch for 2.3 that corrects it to match actual hardware.