From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS31976 209.132.180.0/23 X-Spam-Status: No, score=-4.0 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_EF,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 3BDF71F405 for ; Fri, 21 Dec 2018 01:19:54 +0000 (UTC) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:cc:subject:in-reply-to:message-id :references:mime-version:content-type; q=dns; s=default; b=KH8q+ 0Esyy5siMIiBY5RChXK20zviydu9imu5RnovFyaYGCzAKnSBki0SA8J8UNIexfnk 2OfUspoEJM/nXLoimC7sgKw+qbn9v39CBW0Le77TA8UFln8GoJTuwc8wZIWLmixQ MXy9aau6SWm7sWWQeUNFvrY88vlVXNZhDHdeJQ= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:date:from:to:cc:subject:in-reply-to:message-id :references:mime-version:content-type; s=default; bh=A6kLqRT9Sov th5uOTn2rvyPbW/I=; b=R3H21uWH8r1GhAP52xcvnSXegjcK278fkJQXbVSa9s6 kpB3ZEr/nGjiSzjiKlUIW6HzkPS0gduR7wOVSW9s6IoFW4vgCd4xbOTnZu/cOa3c WvwD/X4P/i8TZuz+OWxx/I8SbDANGffoqB5/8Cu+yivPVb7RoCekIWDiZOkHnYR4 = Received: (qmail 22977 invoked by alias); 21 Dec 2018 01:19:51 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Received: (qmail 22967 invoked by uid 89); 21 Dec 2018 01:19:50 -0000 Authentication-Results: sourceware.org; auth=none X-HELO: relay1.mentorg.com Date: Fri, 21 Dec 2018 01:19:37 +0000 From: Joseph Myers To: Vineet Gupta CC: Claudiu Zissulescu , , Subject: Re: [PATCH 07/21] ARC: math soft float support In-Reply-To: Message-ID: References: <1545167083-16764-1-git-send-email-vgupta@synopsys.com> <1545167083-16764-8-git-send-email-vgupta@synopsys.com> User-Agent: Alpine 2.21 (DEB 202 2017-01-01) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" On Thu, 20 Dec 2018, Vineet Gupta wrote: > I'm still ramping up on hard-float, so pardon some of my naivety. It seems the > function calling convention is no different for soft-float vs. hard-float. We have > a single register file (hard FP instructions inherently use an additional > accumulator but that isn't really passed around so doesn't affect calling > convention). Other than that SP values go normally in a reg, DP go in reg pair > just as any 64bit value. If you have only a single register file and the same calling convention - and all struct layouts etc. are also the same - then indeed that would be a single ABI (meaning that you only need one dynamic linker name for ARC rather than two, if you only support one endianness). (On architectures with separate register files, jmp_buf, ucontext etc. might sometimes differ between hard and soft float, although often the space is still there in the soft-float case, just not used.) The ARM and RISC-V cases are ones where there are separate hard-float and soft-float calling conventions - but *also* support for using hardware floating point with the soft-float calling convention. If you do have a single ABI, that indicates having bits/fenv.h contents unconditional (because a soft-float compilation might legitimately end up linking with a hard-float libm) - and thus indeed needing the internal headers to disable certain math tests for soft-float. fpu_control.h contents would still be conditional, however. -- Joseph S. Myers joseph@codesourcery.com