From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS17314 8.43.84.0/22 X-Spam-Status: No, score=-3.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 02FB21F953 for ; Tue, 9 Nov 2021 19:22:10 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 13F113857C56 for ; Tue, 9 Nov 2021 19:22:09 +0000 (GMT) Received: from mail-qt1-x82b.google.com (mail-qt1-x82b.google.com [IPv6:2607:f8b0:4864:20::82b]) by sourceware.org (Postfix) with ESMTPS id 5E2153858404 for ; Tue, 9 Nov 2021 19:21:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5E2153858404 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bluespec.com Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=bluespec.com Received: by mail-qt1-x82b.google.com with SMTP id q14so1388874qtx.10 for ; Tue, 09 Nov 2021 11:21:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bluespec-com.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:mail-followup-to:references :mime-version:content-disposition:in-reply-to; bh=M89zshu58NIhP/T7LxTd5dGxmxxDsf3KsiBV6k4cTWI=; b=7G4OsKblHNx0DqkP9ii0oyOAvo/5sNP6fAgDz2uMn8HOleAzBdz/KhIN+9WnCiU00t 0WPHF/EWTvqrB+pOO01A/TyaKaQadwz7r3MBp3RFYlQ1dvRXXMFfzTMNpn5fcP49Yf/B EVAA3hZwZ2WUDT2gBf7TmlIMmg2OYYLUGy1h6Do/PZEc+U/9vOzgxpfQuhVzx3KN2YfD rNkEwVCdDT2Q2SOLJSr43S+/2Kn+Yw1RZ+bX8gLhZUSsI7eNl85Ptq/8dVz7ILpWFzgY E5hO3xvT7C9RHlnr1fhLnYDVOQm23pxNM5zl6mFSoY3GAjPmXkqUdLdcYVidO/KsLO/B NOEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id :mail-followup-to:references:mime-version:content-disposition :in-reply-to; bh=M89zshu58NIhP/T7LxTd5dGxmxxDsf3KsiBV6k4cTWI=; b=f8V9EWzh3qoNpDLDq7xwMptCGVtxD5dvIL80+aS1sJfvzg60KpeBgqKfCDaj8xlYKX xHyD6cLVzjO3U8s4eH0YGyHE2lQRPG6jOBTMdm3oJwb/JdCCk6B9uAOwKiZJAyiWZOfA VT9UMYkUPlVaChFAAUEr7Nxr0p1zHJpMIVv2N3a6JMHaFPN9/8JmIUDmh31qJMLFQ9MI d7jQV6mzOmwI+GR9MYjcv3Epx14uusG8PC95By23ep3RNmLmbrNWCPlxT13nI0g1COXr XV6IuumFIWQLTJEw3lpMA0O8bUHC3ljX3SrLSrQ81Te8ELQuFen0Q/9KIg1CmjLoTgW/ PVuQ== X-Gm-Message-State: AOAM530Payya/7Jc7tjReRriYAi4T8xADjdMSAuR/8v5JHcTYe8UEudB udqYMngiCJhhkZE2DGCW6cTU X-Google-Smtp-Source: ABdhPJx6bkVsdVgPKqNxgAtFERkaoiBn219qO4jIiJpCFjEfpH3gq4+c65AxNeHty251Cx7Ap/Zu+A== X-Received: by 2002:ac8:56f8:: with SMTP id 24mr11184461qtu.352.1636485716009; Tue, 09 Nov 2021 11:21:56 -0800 (PST) Received: from bruce.bluespec.com ([154.3.44.94]) by smtp.gmail.com with ESMTPSA id d3sm13147229qte.4.2021.11.09.11.21.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Nov 2021 11:21:55 -0800 (PST) Date: Tue, 9 Nov 2021 14:21:53 -0500 From: Darius Rad To: Vincent Chen Subject: Re: [RFC patch 0/5] RISC-V: Add vector ISA support Message-ID: Mail-Followup-To: Vincent Chen , libc-alpha@sourceware.org, palmer@dabbelt.com, dj@redhat.com, andrew@sifive.com References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: libc-alpha@sourceware.org, andrew@sifive.com Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On Mon, Sep 13, 2021 at 09:41:13AM +0800, Vincent Chen wrote: > This patchset adds required ports to support RISC-V Vector (RVV) extension. > > Since the length of the vector register in RVV (the theoretical maximum > is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back > up all vector registers in the signal context. This patchset expands the > default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack > size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also > places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the > auxiliary vector to inform user, so user still can know the sutible minimum > signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater > than 128 bytes. > > In addition, according to the specification, the VCSR that combines VXRM and > VXSAT has thread storage duration, so this patchset adds the required user > context operation for it. > > Finally, the RISC-V glibc customized sigcontext.h has been removed in this > patchset. to reduce the synchronization work when new extension support is > introduced to the Linux environment. However, it may bring some backward > incompatible issues. Therefore, I sent an RFC patch > (https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html) > to discuss this modification before this patchset. As I mentioned in the > RFC patch thread, I used OpenEmbeded to evaluate the impact. During the > tests, I didn't get any compiler errors. Therefore, I infer that this > modification may not cause server backward incompatible issues at this > moment. > > 1. The RISC-V V-extension draft v1.0 can be found in > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc > 2. The associated kernel implementation can be found in > http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html > 3. QEMU with RISC-V V-extension support can be found in > https://github.com/sifive/qemu/tree/rvv-1.0 > For the record on libc-alpha, I object to these changes. In particular, the lack of a user space API for the corresponding Linux support. More discussion on linux-riscv: https://lists.infradead.org/pipermail/linux-riscv/2021-September/thread.html#8361 > Vincent Chen (5): > RISC-V: Remove riscv-specific sigcontext.h > RISC-V: Reserve about 5K space in mcontext_t to support future ISA > expansion. > RISC-V: Save and restore VCSR when doing user context switch > RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers > RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment > > sysdeps/riscv/Makefile | 5 +++ > sysdeps/riscv/rtld-global-offsets.sym | 7 ++++ > sysdeps/unix/sysv/linux/riscv/bits/hwcap.h | 31 ++++++++++++++++ > .../unix/sysv/linux/riscv/bits/pthread_stack_min.h | 21 +++++++++++ > sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h | 31 ---------------- > sysdeps/unix/sysv/linux/riscv/bits/sigstack.h | 32 +++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/getcontext.S | 22 +++++++++++- > sysdeps/unix/sysv/linux/riscv/setcontext.S | 22 ++++++++++++ > sysdeps/unix/sysv/linux/riscv/swapcontext.S | 41 ++++++++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/sys/ucontext.h | 2 ++ > .../sysv/linux/riscv/sysconf-pthread_stack_min.h | 39 ++++++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/sysdep.h | 1 + > sysdeps/unix/sysv/linux/riscv/ucontext_i.sym | 6 ++++ > 13 files changed, 228 insertions(+), 32 deletions(-) > create mode 100644 sysdeps/riscv/rtld-global-offsets.sym > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/pthread_stack_min.h > delete mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/sysconf-pthread_stack_min.h > > -- > 2.7.4 >