From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS3215 2.6.0.0/16 X-Spam-Status: No, score=-4.2 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 602D01F8C6 for ; Tue, 27 Jul 2021 19:23:32 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5BF5F383980A for ; Tue, 27 Jul 2021 19:23:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5BF5F383980A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1627413811; bh=NK1Y7qHbKc0tnM0CkJAey79vQBKdtY11pBKX8Ugj+YQ=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=kRgSRvaErG/qGcyxnxLwCkzo9Btp4cNuojYwiW95QlryvdlcCDPA/AOQ3p2U35SwY BdWza8oAlYSgjtnMNxyKfMXkZAI6BBHuu+aJsY/bW7nsXIOHJJpr3X++QrkiU7uhru 0GAfGf++ZqyCI6MoxXdC1XbjZZf3LPSS8b40A2kY= Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id 878C8385743A for ; Tue, 27 Jul 2021 19:23:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 878C8385743A Received: by mail-pj1-x102e.google.com with SMTP id k4-20020a17090a5144b02901731c776526so6122327pjm.4 for ; Tue, 27 Jul 2021 12:23:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=NK1Y7qHbKc0tnM0CkJAey79vQBKdtY11pBKX8Ugj+YQ=; b=GRcw30q+T6GR45VC280pAn6QcPzYQnDhKitR4HuF2MEs9X1siGJzYilaIWLTY0rA2w OzHF5fcUITHaEROvo2WidmEANU3bcbXAfZvxlF62KpBJvbD2V4WsvnJZDIoVjTyZ1ook E4EbyF0klJNujiils256rZyBHLMGIlkSSd3VqcdKNut1L+hjdMyvZGcom938GAOY8zB5 Ub+30Sx7nR+q8pZePjyj/4EcJT99pukxUr8q0Ww/rbWIGkfrkcsZFCwYz9QPMFUwKMUg szPpIV/ZC/SnMFBRv/jQT4RrVVNn0lF+3ZIQ4L34Tw3VTb6xWVnSBmSJwKTUIqEHvK1c nXfA== X-Gm-Message-State: AOAM5324f8yM7PyvfjJEDXjAkiiAvPP2/Vb1I6Tp1WMUV4X1lKSDPtsx kH3VdYB9rA9G1kWhh+7A5ND2xeF0XRqQ7FCq798= X-Google-Smtp-Source: ABdhPJxjiAg+AQNwrNjrEuBMX4RDq/SZ99xmQUe3u/KXMocuvJR/0Vy1guynnTdzlBNmKSZ2ouYjg+UarYW3xv/StGg= X-Received: by 2002:a63:114d:: with SMTP id 13mr25606740pgr.180.1627413789629; Tue, 27 Jul 2021 12:23:09 -0700 (PDT) MIME-Version: 1.0 References: <20210726120055.1089971-1-hjl.tools@gmail.com> In-Reply-To: Date: Tue, 27 Jul 2021 12:22:33 -0700 Message-ID: Subject: [PATCH v3] x86-64: Add Avoid_Short_Distance_REP_MOVSB To: Noah Goldstein Content-Type: multipart/mixed; boundary="000000000000d57f3b05c81fccb6" X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: "H.J. Lu via Libc-alpha" Reply-To: "H.J. Lu" Cc: GNU C Library Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" --000000000000d57f3b05c81fccb6 Content-Type: text/plain; charset="UTF-8" On Tue, Jul 27, 2021 at 12:12 PM Noah Goldstein wrote: > > > > On Tue, Jul 27, 2021 at 12:06 PM H.J. Lu wrote: >> >> On Mon, Jul 26, 2021 at 9:06 PM Noah Goldstein wrote: >> > >> > >> > >> > On Mon, Jul 26, 2021 at 11:11 PM H.J. Lu via Libc-alpha wrote: >> >> >> >> On Mon, Jul 26, 2021 at 7:15 PM Carlos O'Donell wrote: >> >> > >> >> > On 7/26/21 8:00 AM, H.J. Lu via Libc-alpha wrote: >> >> > > commit 3ec5d83d2a237d39e7fd6ef7a0bc8ac4c171a4a5 >> >> > > Author: H.J. Lu >> >> > > Date: Sat Jan 25 14:19:40 2020 -0800 >> >> > > >> >> > > x86-64: Avoid rep movsb with short distance [BZ #27130] >> >> > > introduced some regressions on Intel processors without Fast Short REP >> >> > > MOV (FSRM). Add Avoid_Short_Distance_REP_MOVSB to avoid rep movsb with >> >> > > short distance only on Intel processors with FSRM. bench-memmove-large >> >> > > on Skylake server shows that cycles of __memmove_evex_unaligned_erms are >> >> > > improved for the following data size: >> >> > > >> >> > > before after Improvement >> >> > > length=4127, align1=3, align2=0: 479.38 343.00 28% >> >> > > length=4223, align1=9, align2=5: 405.62 335.50 17% >> >> > > length=8223, align1=3, align2=0: 786.12 495.00 37% >> >> > > length=8319, align1=9, align2=5: 256.69 170.38 33% >> >> > > length=16415, align1=3, align2=0: 1436.88 839.50 41% >> >> > > length=16511, align1=9, align2=5: 1375.50 840.62 39% >> >> > > length=32799, align1=3, align2=0: 2890.00 1850.62 36% >> >> > > length=32895, align1=9, align2=5: 2891.38 1948.62 32% >> >> > > >> >> > > There are no regression on Ice Lake server. >> >> > >> >> > At this point we're waiting on Noah to provide feedback on the performance >> >> > results given the alignment nop insertion you provided as a follow-up patch >> > >> > >> > The results with the padding look good! >> > >> >> >> >> >> >> We are testing 25 byte nop padding now: >> >> >> >> >> >> https://gitlab.com/x86-glibc/glibc/-/commit/de8985640a568786a59576716db54e0749d420e8 >> >> >> > How did you come to the exact padding choice used? >> >> I first replaced the 9 byte instructions: >> >> andl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, >> __x86_string_control(%rip) >> jz 3f >> >> with a 9-byte NOP and reproduced the regression on Tiger Lake. It confirmed >> that the code layout caused the regression. I first tried adding >> ".p2align 4" to >> branch targets and they made no differences. Then I started adding different >> size of nops after >> >> andl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, >> __x86_string_control(%rip) >> jz 3f >> movq %rdi, %rcx >> subq %rsi, %rcx >> jmp 2f >> >> with ".nops N". I started with N == 1 and doubled N in each step. I >> noticed that >> improvement started at N == 32. I started bisecting between 16 and 32: >> >> 1. 24 and 32 are good. >> 2. 24 and 28 are good. >> 3. 25 is the best overall. >> >> >> >> >> > (unless you can confirm this yourself). >> >> > >> >> > Looking forward to a v2 the incorporates the alignment fix (pending Noah's >> >> > comments), and my suggestions below. >> >> >> >> > >> >> > > --- >> >> > > sysdeps/x86/cacheinfo.h | 7 +++++++ >> >> > > sysdeps/x86/cpu-features.c | 5 +++++ >> >> > > .../x86/include/cpu-features-preferred_feature_index_1.def | 1 + >> >> > > sysdeps/x86/sysdep.h | 3 +++ >> >> > > sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S | 5 +++++ >> >> > > 5 files changed, 21 insertions(+) >> >> > > >> >> > > diff --git a/sysdeps/x86/cacheinfo.h b/sysdeps/x86/cacheinfo.h >> >> > > index eba8dbc4a6..174ea38f5b 100644 >> >> > > --- a/sysdeps/x86/cacheinfo.h >> >> > > +++ b/sysdeps/x86/cacheinfo.h >> >> > > @@ -49,6 +49,9 @@ long int __x86_rep_stosb_threshold attribute_hidden = 2048; >> >> > > /* Threshold to stop using Enhanced REP MOVSB. */ >> >> > > long int __x86_rep_movsb_stop_threshold attribute_hidden; >> >> > > >> >> > > +/* String/memory function control. */ >> >> > > +int __x86_string_control attribute_hidden; >> >> > >> >> > Please expand comment. >> >> > >> >> > Suggest: >> >> > >> >> > /* A bit-wise OR of string/memory requirements for optimal performance >> >> > e.g. X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB. These bits >> >> > are used at runtime to tune implementation behavior. */ >> >> > int __x86_string_control attribute_hidden; >> >> >> >> I will fix it in the v2 patch. >> >> >> >> Thanks. >> >> >> >> > > + >> >> > > static void >> >> > > init_cacheinfo (void) >> >> > > { >> >> > > @@ -71,5 +74,9 @@ init_cacheinfo (void) >> >> > > __x86_rep_movsb_threshold = cpu_features->rep_movsb_threshold; >> >> > > __x86_rep_stosb_threshold = cpu_features->rep_stosb_threshold; >> >> > > __x86_rep_movsb_stop_threshold = cpu_features->rep_movsb_stop_threshold; >> >> > > + >> >> > > + if (CPU_FEATURES_ARCH_P (cpu_features, Avoid_Short_Distance_REP_MOVSB)) >> >> > > + __x86_string_control >> >> > > + |= X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB; >> >> > >> >> > OK. >> >> > >> >> > > } >> >> > > #endif >> >> > > diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c >> >> > > index 706a172ba9..645bba6314 100644 >> >> > > --- a/sysdeps/x86/cpu-features.c >> >> > > +++ b/sysdeps/x86/cpu-features.c >> >> > > @@ -555,6 +555,11 @@ init_cpu_features (struct cpu_features *cpu_features) >> >> > > cpu_features->preferred[index_arch_Prefer_AVX2_STRCMP] >> >> > > |= bit_arch_Prefer_AVX2_STRCMP; >> >> > > } >> >> > > + >> >> > > + /* Avoid avoid short distance REP MOVSB on processor with FSRM. */ >> >> > > + if (CPU_FEATURES_CPU_P (cpu_features, FSRM)) >> >> > > + cpu_features->preferred[index_arch_Avoid_Short_Distance_REP_MOVSB] >> >> > > + |= bit_arch_Avoid_Short_Distance_REP_MOVSB; >> >> > >> >> > OK. >> >> > >> >> > > } >> >> > > /* This spells out "AuthenticAMD" or "HygonGenuine". */ >> >> > > else if ((ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65) >> >> > > diff --git a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def >> >> > > index 133aab19f1..d7c93f00c5 100644 >> >> > > --- a/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def >> >> > > +++ b/sysdeps/x86/include/cpu-features-preferred_feature_index_1.def >> >> > > @@ -33,3 +33,4 @@ BIT (Prefer_No_AVX512) >> >> > > BIT (MathVec_Prefer_No_AVX512) >> >> > > BIT (Prefer_FSRM) >> >> > > BIT (Prefer_AVX2_STRCMP) >> >> > > +BIT (Avoid_Short_Distance_REP_MOVSB) >> >> > >> >> > OK. >> >> > >> >> > > diff --git a/sysdeps/x86/sysdep.h b/sysdeps/x86/sysdep.h >> >> > > index 51c069bfe1..35cb90d507 100644 >> >> > > --- a/sysdeps/x86/sysdep.h >> >> > > +++ b/sysdeps/x86/sysdep.h >> >> > > @@ -57,6 +57,9 @@ enum cf_protection_level >> >> > > #define STATE_SAVE_MASK \ >> >> > > ((1 << 1) | (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | (1 << 7)) >> >> > > >> >> > >> >> > Suggest adding: >> >> > >> >> > /* Constants for bits in __x86_string_control: */ >> >> > >> >> > > +/* Avoid short distance REP MOVSB. */ >> >> > > +#define X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB (1 << 0) >> >> > >> >> > OK. >> >> > >> >> > > + >> >> > > #ifdef __ASSEMBLER__ >> >> > > >> >> > > /* Syntactic details of assembler. */ >> >> > > diff --git a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S >> >> > > index a783da5de2..9f02624375 100644 >> >> > > --- a/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S >> >> > > +++ b/sysdeps/x86_64/multiarch/memmove-vec-unaligned-erms.S >> >> > > @@ -325,12 +325,16 @@ L(movsb): >> >> > > /* Avoid slow backward REP MOVSB. */ >> >> > > jb L(more_8x_vec_backward) >> >> > > # if AVOID_SHORT_DISTANCE_REP_MOVSB >> >> > > + andl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, __x86_string_control(%rip) >> >> > > + jz 3f >> >> > >> >> > OK. >> >> > >> >> > > movq %rdi, %rcx >> >> > > subq %rsi, %rcx >> >> > > jmp 2f >> >> > > # endif >> >> > > 1: >> >> > > # if AVOID_SHORT_DISTANCE_REP_MOVSB >> >> > > + andl $X86_STRING_CONTROL_AVOID_SHORT_DISTANCE_REP_MOVSB, __x86_string_control(%rip) >> >> > > + jz 3f >> >> > >> >> > OK. >> >> > >> >> > > movq %rsi, %rcx >> >> > > subq %rdi, %rcx >> >> > > 2: >> >> > > @@ -338,6 +342,7 @@ L(movsb): >> >> > > is N*4GB + [1..63] with N >= 0. */ >> >> > > cmpl $63, %ecx >> >> > > jbe L(more_2x_vec) /* Avoid "rep movsb" if ECX <= 63. */ >> >> > > +3: >> >> > >> >> > OK. >> >> > >> >> > > # endif >> >> > > mov %RDX_LP, %RCX_LP >> >> > > rep movsb >> >> > > >> >> > >> >> > >> >> > -- >> >> > Cheers, >> >> > Carlos. >> >> > >> >> >> >> >> >> -- >> >> H.J. >> >> Here is the v2 patch: >> >> 1. Add a 25-byte NOP padding after JMP for Avoid_Short_Distance_REP_MOVSB, >> which improves bench-memcpy-random performance on Tiger Lake by ~30% > > > I think this may not be due to unrelated factors. I reran the random benchmarks with > the function on a fresh page and entry of the *_erms version at either + 0, 16, 32, 48 > bytes and 1) don't see a universal improvement and 2) believe it's likely that the 30% > you measured is due to unrelated alignment changes. > > "__memcpy_avx_unaligned", "__memcpy_avx_unaligned_erms", "__memcpy_evex_unaligned", "__memcpy_evex_unaligned_erms" > > + 0 Entry Alignment > New: 91824.1, 95460.1, 95063.3, 97998.3 > Old: 99973.7, 100127, 100370, 100049 > > + 16 Entry Alignment > New: 129558, 129916, 122373, 124056 > Old: 125361, 96475.4, 97457.8, 124319 > > + 32 Entry Alignment > New: 95073.7, 92857.8, 90182.2, 92666.3 > Old: 96702.1, 98558.9, 96797.1, 96887.1 > > + 48 Entry Alignment > New: 135161, 134010, 123023, 148589 > Old: 128150, 139029, 98382.2, 122686 > > So the 32 byte/64 byte entry alignment versions seem to favor this change, > but when entry alignment % 16 != 0 this change seems to perform worse. > > I generally think until we understand why the byte padding is necessary its > probably a mistake to include it unless its a benefit in actual SPEC2017. > > My general intuition is that this is an issue with the benchmarks themselves > so I support the change w.o the padding. Here is the v3 patch without the padding. OK for master? > >> 2. Update comments for __x86_string_control. >> >> >> -- >> H.J. -- H.J. --000000000000d57f3b05c81fccb6 Content-Type: text/x-patch; charset="US-ASCII"; name="v3-0001-x86-64-Add-Avoid_Short_Distance_REP_MOVSB.patch" Content-Disposition: attachment; filename="v3-0001-x86-64-Add-Avoid_Short_Distance_REP_MOVSB.patch" Content-Transfer-Encoding: base64 Content-ID: X-Attachment-Id: f_krmg31sc0 RnJvbSA4YWUxYjkxNGU4YzBlMGY1ODI0OTkzN2EyZjM0OGM5YjI5N2Y3MGY2IE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiAiSC5KLiBMdSIgPGhqbC50b29sc0BnbWFpbC5jb20+CkRhdGU6 IFRodSwgMjIgSnVsIDIwMjEgMjA6MjY6MjUgLTA3MDAKU3ViamVjdDogW1BBVENIIHYzXSB4ODYt NjQ6IEFkZCBBdm9pZF9TaG9ydF9EaXN0YW5jZV9SRVBfTU9WU0IKCmNvbW1pdCAzZWM1ZDgzZDJh MjM3ZDM5ZTdmZDZlZjdhMGJjOGFjNGMxNzFhNGE1CkF1dGhvcjogSC5KLiBMdSA8aGpsLnRvb2xz QGdtYWlsLmNvbT4KRGF0ZTogICBTYXQgSmFuIDI1IDE0OjE5OjQwIDIwMjAgLTA4MDAKCiAgICB4 ODYtNjQ6IEF2b2lkIHJlcCBtb3ZzYiB3aXRoIHNob3J0IGRpc3RhbmNlIFtCWiAjMjcxMzBdCgpp bnRyb2R1Y2VkIHNvbWUgcmVncmVzc2lvbnMgb24gSW50ZWwgcHJvY2Vzc29ycyB3aXRob3V0IEZh c3QgU2hvcnQgUkVQCk1PViAoRlNSTSkuICBBZGQgQXZvaWRfU2hvcnRfRGlzdGFuY2VfUkVQX01P VlNCIHRvIGF2b2lkIHJlcCBtb3ZzYiB3aXRoCnNob3J0IGRpc3RhbmNlIG9ubHkgb24gSW50ZWwg cHJvY2Vzc29ycyB3aXRoIEZTUk0uICBiZW5jaC1tZW1tb3ZlLWxhcmdlCm9uIFNreWxha2Ugc2Vy dmVyIHNob3dzIHRoYXQgY3ljbGVzIG9mIF9fbWVtbW92ZV9ldmV4X3VuYWxpZ25lZF9lcm1zCmlt cHJvdmVzIGZvciB0aGUgZm9sbG93aW5nIGRhdGEgc2l6ZToKCiAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICBiZWZvcmUgICAgYWZ0ZXIgICAgSW1wcm92ZW1lbnQKbGVuZ3RoPTQxMjcs IGFsaWduMT0zLCBhbGlnbjI9MDogIDQ3OS4zOCAgICAzNDkuMjUgICAgICAyNyUKbGVuZ3RoPTQy MjMsIGFsaWduMT05LCBhbGlnbjI9NTogIDQwNS42MiAgICAzMzMuMjUgICAgICAxOCUKbGVuZ3Ro PTgyMjMsIGFsaWduMT0zLCBhbGlnbjI9MDogIDc4Ni4xMiAgICA0OTYuMzggICAgICAzNyUKbGVu Z3RoPTgzMTksIGFsaWduMT05LCBhbGlnbjI9NTogIDcyNy41MCAgICA1MDEuMzggICAgICAzMSUK bGVuZ3RoPTE2NDE1LCBhbGlnbjE9MywgYWxpZ24yPTA6IDE0MzYuODggICA4NDAuMDAgICAgICA0 MSUKbGVuZ3RoPTE2NTExLCBhbGlnbjE9OSwgYWxpZ24yPTU6IDEzNzUuNTAgICA4MzYuMzggICAg ICAzOSUKbGVuZ3RoPTMyNzk5LCBhbGlnbjE9MywgYWxpZ24yPTA6IDI4OTAuMDAgICAxODYwLjEy ICAgICAzNiUKbGVuZ3RoPTMyODk1LCBhbGlnbjE9OSwgYWxpZ24yPTU6IDI4OTEuMzggICAxOTMx Ljg4ICAgICAzMyUKLS0tCiBzeXNkZXBzL3g4Ni9jYWNoZWluZm8uaCAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICB8IDkgKysrKysrKysrCiBzeXNkZXBzL3g4Ni9jcHUtZmVhdHVyZXMu YyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB8IDUgKysrKysKIC4uLi9pbmNsdWRlL2Nw dS1mZWF0dXJlcy1wcmVmZXJyZWRfZmVhdHVyZV9pbmRleF8xLmRlZiAgIHwgMSArCiBzeXNkZXBz L3g4Ni9zeXNkZXAuaCAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICB8IDUgKysr KysKIHN5c2RlcHMveDg2XzY0L211bHRpYXJjaC9tZW1tb3ZlLXZlYy11bmFsaWduZWQtZXJtcy5T ICAgIHwgNSArKysrKwogNSBmaWxlcyBjaGFuZ2VkLCAyNSBpbnNlcnRpb25zKCspCgpkaWZmIC0t Z2l0IGEvc3lzZGVwcy94ODYvY2FjaGVpbmZvLmggYi9zeXNkZXBzL3g4Ni9jYWNoZWluZm8uaApp bmRleCBlYmE4ZGJjNGE2Li40MWQyYzgxMzY5IDEwMDY0NAotLS0gYS9zeXNkZXBzL3g4Ni9jYWNo ZWluZm8uaAorKysgYi9zeXNkZXBzL3g4Ni9jYWNoZWluZm8uaApAQCAtNDksNiArNDksMTEgQEAg bG9uZyBpbnQgX194ODZfcmVwX3N0b3NiX3RocmVzaG9sZCBhdHRyaWJ1dGVfaGlkZGVuID0gMjA0 ODsKIC8qIFRocmVzaG9sZCB0byBzdG9wIHVzaW5nIEVuaGFuY2VkIFJFUCBNT1ZTQi4gICovCiBs b25nIGludCBfX3g4Nl9yZXBfbW92c2Jfc3RvcF90aHJlc2hvbGQgYXR0cmlidXRlX2hpZGRlbjsK IAorLyogQSBiaXQtd2lzZSBPUiBvZiBzdHJpbmcvbWVtb3J5IHJlcXVpcmVtZW50cyBmb3Igb3B0 aW1hbCBwZXJmb3JtYW5jZQorICAgZS5nLiBYODZfU1RSSU5HX0NPTlRST0xfQVZPSURfU0hPUlRf RElTVEFOQ0VfUkVQX01PVlNCLiAgVGhlc2UgYml0cworICAgYXJlIHVzZWQgYXQgcnVudGltZSB0 byB0dW5lIGltcGxlbWVudGF0aW9uIGJlaGF2aW9yLiAgKi8KK2ludCBfX3g4Nl9zdHJpbmdfY29u dHJvbCBhdHRyaWJ1dGVfaGlkZGVuOworCiBzdGF0aWMgdm9pZAogaW5pdF9jYWNoZWluZm8gKHZv aWQpCiB7CkBAIC03MSw1ICs3Niw5IEBAIGluaXRfY2FjaGVpbmZvICh2b2lkKQogICBfX3g4Nl9y ZXBfbW92c2JfdGhyZXNob2xkID0gY3B1X2ZlYXR1cmVzLT5yZXBfbW92c2JfdGhyZXNob2xkOwog ICBfX3g4Nl9yZXBfc3Rvc2JfdGhyZXNob2xkID0gY3B1X2ZlYXR1cmVzLT5yZXBfc3Rvc2JfdGhy ZXNob2xkOwogICBfX3g4Nl9yZXBfbW92c2Jfc3RvcF90aHJlc2hvbGQgPSAgY3B1X2ZlYXR1cmVz LT5yZXBfbW92c2Jfc3RvcF90aHJlc2hvbGQ7CisKKyAgaWYgKENQVV9GRUFUVVJFU19BUkNIX1Ag KGNwdV9mZWF0dXJlcywgQXZvaWRfU2hvcnRfRGlzdGFuY2VfUkVQX01PVlNCKSkKKyAgICBfX3g4 Nl9zdHJpbmdfY29udHJvbAorICAgICAgfD0gWDg2X1NUUklOR19DT05UUk9MX0FWT0lEX1NIT1JU X0RJU1RBTkNFX1JFUF9NT1ZTQjsKIH0KICNlbmRpZgpkaWZmIC0tZ2l0IGEvc3lzZGVwcy94ODYv Y3B1LWZlYXR1cmVzLmMgYi9zeXNkZXBzL3g4Ni9jcHUtZmVhdHVyZXMuYwppbmRleCA3MDZhMTcy YmE5Li42NDViYmE2MzE0IDEwMDY0NAotLS0gYS9zeXNkZXBzL3g4Ni9jcHUtZmVhdHVyZXMuYwor KysgYi9zeXNkZXBzL3g4Ni9jcHUtZmVhdHVyZXMuYwpAQCAtNTU1LDYgKzU1NSwxMSBAQCBpbml0 X2NwdV9mZWF0dXJlcyAoc3RydWN0IGNwdV9mZWF0dXJlcyAqY3B1X2ZlYXR1cmVzKQogCSAgICBj cHVfZmVhdHVyZXMtPnByZWZlcnJlZFtpbmRleF9hcmNoX1ByZWZlcl9BVlgyX1NUUkNNUF0KIAkg ICAgICB8PSBiaXRfYXJjaF9QcmVmZXJfQVZYMl9TVFJDTVA7CiAJfQorCisgICAgICAvKiBBdm9p ZCBhdm9pZCBzaG9ydCBkaXN0YW5jZSBSRVAgTU9WU0Igb24gcHJvY2Vzc29yIHdpdGggRlNSTS4g ICovCisgICAgICBpZiAoQ1BVX0ZFQVRVUkVTX0NQVV9QIChjcHVfZmVhdHVyZXMsIEZTUk0pKQor CWNwdV9mZWF0dXJlcy0+cHJlZmVycmVkW2luZGV4X2FyY2hfQXZvaWRfU2hvcnRfRGlzdGFuY2Vf UkVQX01PVlNCXQorCSAgfD0gYml0X2FyY2hfQXZvaWRfU2hvcnRfRGlzdGFuY2VfUkVQX01PVlNC OwogICAgIH0KICAgLyogVGhpcyBzcGVsbHMgb3V0ICJBdXRoZW50aWNBTUQiIG9yICJIeWdvbkdl bnVpbmUiLiAgKi8KICAgZWxzZSBpZiAoKGVieCA9PSAweDY4NzQ3NTQxICYmIGVjeCA9PSAweDQ0 NGQ0MTYzICYmIGVkeCA9PSAweDY5NzQ2ZTY1KQpkaWZmIC0tZ2l0IGEvc3lzZGVwcy94ODYvaW5j bHVkZS9jcHUtZmVhdHVyZXMtcHJlZmVycmVkX2ZlYXR1cmVfaW5kZXhfMS5kZWYgYi9zeXNkZXBz L3g4Ni9pbmNsdWRlL2NwdS1mZWF0dXJlcy1wcmVmZXJyZWRfZmVhdHVyZV9pbmRleF8xLmRlZgpp bmRleCAxMzNhYWIxOWYxLi5kN2M5M2YwMGM1IDEwMDY0NAotLS0gYS9zeXNkZXBzL3g4Ni9pbmNs dWRlL2NwdS1mZWF0dXJlcy1wcmVmZXJyZWRfZmVhdHVyZV9pbmRleF8xLmRlZgorKysgYi9zeXNk ZXBzL3g4Ni9pbmNsdWRlL2NwdS1mZWF0dXJlcy1wcmVmZXJyZWRfZmVhdHVyZV9pbmRleF8xLmRl ZgpAQCAtMzMsMyArMzMsNCBAQCBCSVQgKFByZWZlcl9Ob19BVlg1MTIpCiBCSVQgKE1hdGhWZWNf UHJlZmVyX05vX0FWWDUxMikKIEJJVCAoUHJlZmVyX0ZTUk0pCiBCSVQgKFByZWZlcl9BVlgyX1NU UkNNUCkKK0JJVCAoQXZvaWRfU2hvcnRfRGlzdGFuY2VfUkVQX01PVlNCKQpkaWZmIC0tZ2l0IGEv c3lzZGVwcy94ODYvc3lzZGVwLmggYi9zeXNkZXBzL3g4Ni9zeXNkZXAuaAppbmRleCA1MWMwNjli ZmUxLi5jYWMxZDc2MmZiIDEwMDY0NAotLS0gYS9zeXNkZXBzL3g4Ni9zeXNkZXAuaAorKysgYi9z eXNkZXBzL3g4Ni9zeXNkZXAuaApAQCAtNTcsNiArNTcsMTEgQEAgZW51bSBjZl9wcm90ZWN0aW9u X2xldmVsCiAjZGVmaW5lIFNUQVRFX1NBVkVfTUFTSyBcCiAgICgoMSA8PCAxKSB8ICgxIDw8IDIp IHwgKDEgPDwgMykgfCAoMSA8PCA1KSB8ICgxIDw8IDYpIHwgKDEgPDwgNykpCiAKKy8qIENvbnN0 YW50cyBmb3IgYml0cyBpbiBfX3g4Nl9zdHJpbmdfY29udHJvbDogICovCisKKy8qIEF2b2lkIHNo b3J0IGRpc3RhbmNlIFJFUCBNT1ZTQi4gICovCisjZGVmaW5lIFg4Nl9TVFJJTkdfQ09OVFJPTF9B Vk9JRF9TSE9SVF9ESVNUQU5DRV9SRVBfTU9WU0IJKDEgPDwgMCkKKwogI2lmZGVmCV9fQVNTRU1C TEVSX18KIAogLyogU3ludGFjdGljIGRldGFpbHMgb2YgYXNzZW1ibGVyLiAgKi8KZGlmZiAtLWdp dCBhL3N5c2RlcHMveDg2XzY0L211bHRpYXJjaC9tZW1tb3ZlLXZlYy11bmFsaWduZWQtZXJtcy5T IGIvc3lzZGVwcy94ODZfNjQvbXVsdGlhcmNoL21lbW1vdmUtdmVjLXVuYWxpZ25lZC1lcm1zLlMK aW5kZXggYTc4M2RhNWRlMi4uOWYwMjYyNDM3NSAxMDA2NDQKLS0tIGEvc3lzZGVwcy94ODZfNjQv bXVsdGlhcmNoL21lbW1vdmUtdmVjLXVuYWxpZ25lZC1lcm1zLlMKKysrIGIvc3lzZGVwcy94ODZf NjQvbXVsdGlhcmNoL21lbW1vdmUtdmVjLXVuYWxpZ25lZC1lcm1zLlMKQEAgLTMyNSwxMiArMzI1 LDE2IEBAIEwobW92c2IpOgogCS8qIEF2b2lkIHNsb3cgYmFja3dhcmQgUkVQIE1PVlNCLiAgKi8K IAlqYglMKG1vcmVfOHhfdmVjX2JhY2t3YXJkKQogIyBpZiBBVk9JRF9TSE9SVF9ESVNUQU5DRV9S RVBfTU9WU0IKKwlhbmRsCSRYODZfU1RSSU5HX0NPTlRST0xfQVZPSURfU0hPUlRfRElTVEFOQ0Vf UkVQX01PVlNCLCBfX3g4Nl9zdHJpbmdfY29udHJvbCglcmlwKQorCWp6CTNmCiAJbW92cQklcmRp LCAlcmN4CiAJc3VicQklcnNpLCAlcmN4CiAJam1wCTJmCiAjIGVuZGlmCiAxOgogIyBpZiBBVk9J RF9TSE9SVF9ESVNUQU5DRV9SRVBfTU9WU0IKKwlhbmRsCSRYODZfU1RSSU5HX0NPTlRST0xfQVZP SURfU0hPUlRfRElTVEFOQ0VfUkVQX01PVlNCLCBfX3g4Nl9zdHJpbmdfY29udHJvbCglcmlwKQor CWp6CTNmCiAJbW92cQklcnNpLCAlcmN4CiAJc3VicQklcmRpLCAlcmN4CiAyOgpAQCAtMzM4LDYg KzM0Miw3IEBAIEwobW92c2IpOgogICAgaXMgTio0R0IgKyBbMS4uNjNdIHdpdGggTiA+PSAwLiAg Ki8KIAljbXBsCSQ2MywgJWVjeAogCWpiZQlMKG1vcmVfMnhfdmVjKQkvKiBBdm9pZCAicmVwIG1v dnNiIiBpZiBFQ1ggPD0gNjMuICAqLworMzoKICMgZW5kaWYKIAltb3YJJVJEWF9MUCwgJVJDWF9M UAogCXJlcCBtb3ZzYgotLSAKMi4zMS4xCgo= --000000000000d57f3b05c81fccb6--