From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_REPLYTO_END_DIGIT, MAILING_LIST_MULTI,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 7750D1F5AE for ; Sat, 11 Jul 2020 15:59:51 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 35CC13857C42; Sat, 11 Jul 2020 15:59:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 35CC13857C42 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1594483190; bh=/AZVgFIJ8nqdvZI5Pm/KWKNqKum+ihAJvdKaS6pxjA4=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=vH7cZVvYf8J02DfByaTAtDN4S4srXo4hwnjyshkuGXsKcR6B2NwZ2Ws9K81KOsOUz nRSMx/k7xm2P70cSHAk275keMbTVdkhQwBns1QOZcURiKwHf2NQdDNlW69NtO+xIrd y5XSzZ/g0DGs7t53IIjw9wtX/A8fhZYx5kPTCNBY= Received: from mail-il1-x141.google.com (mail-il1-x141.google.com [IPv6:2607:f8b0:4864:20::141]) by sourceware.org (Postfix) with ESMTPS id 7E62B3857C42 for ; Sat, 11 Jul 2020 15:59:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7E62B3857C42 Received: by mail-il1-x141.google.com with SMTP id p15so22376ilh.13 for ; Sat, 11 Jul 2020 08:59:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=/AZVgFIJ8nqdvZI5Pm/KWKNqKum+ihAJvdKaS6pxjA4=; b=NkEjrUqhwXbF6JKr7nO4wAO7CcLZ7oL3xRdxryi53aAdfEtkxbGczzSqTkPVim2jkP zx41YVXv+tKUwPjQvIhc5VqO/BV9vTNv6p4bUSnSSz0+xG2WTmqrELv4epzc36qn8khc xFbSq+dEF4fJRSY7R6QJQDW+NjF71txJPFC3K00v4XZXGHLgOHOGRWTAYSbXEqPP65Vz KDuUhPND50NYi7kx4QOJeGamHFi7V/lReZPtPNhICvyNhwYIsJyNawLjissK5SAGyEeJ 2unp4swrIFO0h5ixqP3q8Rpm04+XiwqEXy2sfFmBtcISJlWF+57W7PjjtPSBlEadhX9H SULw== X-Gm-Message-State: AOAM532ZMOa0xjSxc1bRXx57IY+RSH2OsFo7nThewIxTC/RHAYRcm+Uv kfXb0l/+6tDYElFv84t0j1WOBSbItmXOsfJKbDc= X-Google-Smtp-Source: ABdhPJyTM0RPdqvpzyJ3W43Cb0I7JZjA8ng/yPQ15ikQlLDywS03JmU4Mxvz2UsDWpahwuXOqTxzY4499NhF0wbKxvY= X-Received: by 2002:a05:6e02:d51:: with SMTP id h17mr58110748ilj.131.1594483186973; Sat, 11 Jul 2020 08:59:46 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: Date: Sat, 11 Jul 2020 08:49:52 -0700 Message-ID: Subject: Re: [PATCH v2 10/18] RISC-V: Hard float support for 32-bit To: "Maciej W. Rozycki" Content-Type: text/plain; charset="UTF-8" X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Alistair Francis via Libc-alpha Reply-To: Alistair Francis Cc: GNU C Library , Alistair Francis Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" On Fri, Jul 10, 2020 at 5:49 PM Maciej W. Rozycki via Libc-alpha wrote: > > On Wed, 3 Jun 2020, Alistair Francis via Libc-alpha wrote: > > > This patch contains hardware floating-point support for the RV32IF and > > RV32IFD > > Full stop please. Fixed. > > > diff --git a/sysdeps/riscv/rv32/rvd/s_lrint.c b/sysdeps/riscv/rv32/rvd/s_lrint.c > > new file mode 100644 > > index 0000000000..df406aacb6 > > --- /dev/null > > +++ b/sysdeps/riscv/rv32/rvd/s_lrint.c > > @@ -0,0 +1,31 @@ > > +/* lrint(). RISC-V version. > > I think this has to mention this is the 32-bit version somehow, like > "32-bit RISC-V" or suchlike ("RV32" might be too cryptic/slang). Feel > free to find a better wording (I'm not particularly happy to start a > sentence with a number). Fixed. > > > + Copyright (C) 2017-2020 Free Software Foundation, Inc. > > Again, 2020 only, and likewise throughout. Also I missed one case in > 01/18 and may have elsewhere, please double-check the remaining patches. Fixed in the whole series. > > Otherwise OK as far as code already proposed for this change is > concerned. Thanks > > What about the other math functions though? We have a lot of optimised > versions in `sysdeps/riscv/rv64/rv{f,d}/', which seem suitable for RV32 as > it stands, such as `s_llrintf.c' or `s_nearbyint.c'. Instead we build > generic `sysdeps/ieee754/{flt-32,dbl-64}/' variants. I haven't looked into the others, but I think you are right and this can be improved. > > Shouldn't we also move the XLEN-agnostic optimised functions to > `sysdeps/riscv/rv{f,d}/' with this change? I think we only need to keep > those that use the `long int' type at the interface in the XLEN-specific > directory. They are all xlen dependent though. All of the 64-bit ones use fcvt.l.d (or something similar) which doesn't exist on RV32. Although the functions end up being the same, the actual assembly instruction called is different. We can look at consolidating them into a single file and do a xlen/__WORDSIZE macro check. At this stage in glibc development I don't really want to change the floating point helpers. Can we leave this as is and then for the next release I can consolidate all of these into single files that do xlen/__WORDSIZE #ifdefs? That way we will just have a single file (for each operation) for RISC-V that will call a different assembly instruction based on xlen or __WORDSIZE. Alistair > > Maciej