From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS17314 8.43.84.0/22 X-Spam-Status: No, score=-4.2 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 86B291F8C6 for ; Thu, 1 Jul 2021 23:06:43 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8B77939724AC for ; Thu, 1 Jul 2021 23:06:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8B77939724AC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1625180802; bh=1Uox1S0PPw09WQD8EX1NDH42bChfcl4372Wv5z2n+Ys=; h=References:In-Reply-To:Date:Subject:To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=wz0H8E9CGqrBu3yJ5JLiNRVpQrjQMa2/ayTqVF7OdRKcIJC2yzz9+jMBUdGtyaEBQ 63V7dRENx2bd4xal4ulWZ9xtUPrGrxhDgoVe3YxD8nsZdJWlHGUfPWQ1FuQXy09EGx dYAGs4CvxW+9Pu1PQ/BJmoMm+b+Q53AK4P93+m8g= Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 12417397203A for ; Thu, 1 Jul 2021 23:05:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 12417397203A Received: by mail-ej1-x62c.google.com with SMTP id hp26so388715ejc.6 for ; Thu, 01 Jul 2021 16:05:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=YDOcTqHsf3nBq3DKz31gwHD9oNIGiG1U4rbWz/cnjk4=; b=QODQ6YK/WC3KzjgT+PV/HrFcRGMnSgCKWAPMc7ZQ79bjSvj25mbGovGGFqxT406tNm J+T2F3emmS3qo3RcYVDUZSGg4zwrmAb39bC5/UyR/bVAiCPcAltnxo7eqwW74K/G6vqA oI5RjJHLbNz67pGvUNylSX02dZwto147TbLLTp/F9LVJYzuq7V2y7ghhWKqM7drTQXvy EDCJvp2MeYHYhdCmZ5rfY+t3RfvBi30xrb7fyxgJrA2UC03TtIQioXmuf1giDx+x7iip 4U/eIVG1vIzRqXTZSOpVghlUdQkHxrzuyzSOM4U7RT80wlEqN4cHrIokiMr0TZEH3+Xg nCAA== X-Gm-Message-State: AOAM533AZwjvzjyNgR2cQkHJBo1XYLI3HyYMMnuS7hUX/Ok2jXPnk7kL a9PyyGyhsqxottpqpZkxrDRlo7dz7GoiXQrWaW4= X-Google-Smtp-Source: ABdhPJwka2cGxAyEXk86l+syApM/6Jrpo7XpdMLa0e5vvFQetZhAFEv/tzEupFOmJxoM0ZOqYWDE7SsupnVGCtxHtLI= X-Received: by 2002:a17:907:3c81:: with SMTP id gl1mr2350637ejc.136.1625180722125; Thu, 01 Jul 2021 16:05:22 -0700 (PDT) MIME-Version: 1.0 References: <20210701210537.51272-1-hjl.tools@gmail.com> In-Reply-To: Date: Thu, 1 Jul 2021 16:05:10 -0700 Message-ID: Subject: Re: [llvm-dev] [PATCH] Add optional _Float16 support To: "H.J. Lu" Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Craig Topper via Libc-alpha Reply-To: Craig Topper Cc: llvm-dev , GNU C Library , GCC Patches , IA32 System V Application Binary Interface , Joseph Myers Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On Thu, Jul 1, 2021 at 4:02 PM H.J. Lu via llvm-dev wrote: > On Thu, Jul 1, 2021 at 3:40 PM Joseph Myers > wrote: > > > > On Thu, 1 Jul 2021, H.J. Lu wrote: > > > > > BTW, _Float16 software emulation may require more than just SSE > > > since we need to do _Float16 load and store with XMM registers. > > > There is no 16bit load/store for XMM registers without AVX512FP16. > > > > You should be able to make the move go via general-purpose registers (for > > example) if you can't do a direct 16-bit load/store for XMM registers. > > > > There is no 16bit move between GPRs and XMM registers without > AVX512FP16. > > Isn't PINSRW supported since SSE1? > > -- > H.J. > _______________________________________________ > LLVM Developers mailing list > llvm-dev@lists.llvm.org > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >