From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS3215 2.6.0.0/16 X-Spam-Status: No, score=-3.7 required=3.0 tests=AWL,BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id D602E1F8C8 for ; Thu, 16 Sep 2021 09:26:15 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 14AC8385782A for ; Thu, 16 Sep 2021 09:26:13 +0000 (GMT) Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by sourceware.org (Postfix) with ESMTPS id E438F3858D3C for ; Thu, 16 Sep 2021 09:26:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E438F3858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pf1-x436.google.com with SMTP id q22so5418366pfu.0 for ; Thu, 16 Sep 2021 02:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=1w57X8WFpM3VCqRIY/dh/h/hC/0zCd1r8nCN4Clsoz4=; b=jMpZ2OQqkgbcXOlAn2pcau6xtCcpY8m+pzBBd+TmjWgl2p/aLXJJQFZQt5I2Y938zL xunEYiREQdbhINDQp6U/UXe0JrAxXUDDMSDbaveQNtHA1yFzf0Ct/0CeKfnxJ92rzs35 YyEJ1m2IX5HYqw7/jGVXkwyu7RMPw+1pZLR4PilK2zwPCJsj5DZTRlR3akJcD4eLuETc krazrH0o8C1Jfvjmvo6zPzfpPfnPMuUVos+8FHO3iSg9C2XzsaOcliW91ahiYZaq+bxd RGmxwo+nlsrbz7B8ofZ6u3RI5sHS0/wQ8twRcQPnLRHBbqvoNYtJsBzOqBQArBMpciOO tWUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=1w57X8WFpM3VCqRIY/dh/h/hC/0zCd1r8nCN4Clsoz4=; b=0B52SKLNFewxUr2dVxfIpnVfW3VppLWaOvbivCo7QiXcTEn05a5FbPSKghT+kJ2wdw QKE4HQsgFPxajRRf/9kejlrw8XvVoms21Js4Xa9YD9aouwkRA64cXIacmY6k/ejnibG9 4/Gp5X2NWLz/EYWWwb5m07XJK485vYoNVy0JwATP3Xn+gtHQgQIXXWgHyVKtzWBvZ68F 1XN3FlDoHMa82aTIlfe8aIIVQ/q6s3h0vy4NDxW8wCf304VM0ri8eC1Vo8D0k3soe36i nLHworFpprD8t60Uk4XKjMM/tFXbH6aH+oCoz5GVwKgvosH/eUtzUYSTPGZxNrHiBRDh N5aA== X-Gm-Message-State: AOAM532h2SjqNxd2rsjQ+RaZTrl+d5VD7dS67NvyeFlJpg1zdZG33/Rx k+dZSmhF8c8PILD/tJjgG8pwMiKTdm5V5Bj78eGRuQ== X-Google-Smtp-Source: ABdhPJzErmIhLKYNxTAhxH6lAybezIBcLpXmdtHYts/fgf2eKVGdN28U9AsGOu1jgUabB7xvTf44IAOfIEHqZEAcqwk= X-Received: by 2002:a65:6398:: with SMTP id h24mr4012434pgv.367.1631784360773; Thu, 16 Sep 2021 02:26:00 -0700 (PDT) MIME-Version: 1.0 References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> <1631497278-29829-5-git-send-email-vincent.chen@sifive.com> <20210913135142.GK13220@brightrain.aerifal.cx> In-Reply-To: <20210913135142.GK13220@brightrain.aerifal.cx> From: Vincent Chen Date: Thu, 16 Sep 2021 17:25:50 +0800 Message-ID: Subject: Re: [RFC patch 4/5] RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers To: Rich Felker Content-Type: text/plain; charset="UTF-8" X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: GNU C Library , Andrew Waterman Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On Mon, Sep 13, 2021 at 9:51 PM Rich Felker wrote: > > On Mon, Sep 13, 2021 at 09:41:17AM +0800, Vincent Chen wrote: > > As using RVV extension, the original MINSIGSTKSZ is not enough to > > back up all RVV registers for the normal case. Therefore, the MINSIGSTKSZ > > is expanded to about 5K and the SIGSTKSZ is expanded to about 16K. This > > space is enough for the case that the VLENB of a vector register is 128 > > bytes. For the case that VLENB > 128 bytes, users can use > > sysconf (_SC_MINSIGSTKSZ) and sysconf (_SC_SIGSTKSZ) to get the > > appropriate signal stack size. > > --- > > sysdeps/unix/sysv/linux/riscv/bits/sigstack.h | 32 +++++++++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > > > > diff --git a/sysdeps/unix/sysv/linux/riscv/bits/sigstack.h b/sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > > new file mode 100644 > > index 0000000..c18512f > > --- /dev/null > > +++ b/sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > > @@ -0,0 +1,32 @@ > > +/* sigstack, sigaltstack definitions. > > + Copyright (C) 2021 Free Software Foundation, Inc. > > + This file is part of the GNU C Library. > > + > > + The GNU C Library is free software; you can redistribute it and/or > > + modify it under the terms of the GNU Lesser General Public > > + License as published by the Free Software Foundation; either > > + version 2.1 of the License, or (at your option) any later version. > > + > > + The GNU C Library is distributed in the hope that it will be useful, > > + but WITHOUT ANY WARRANTY; without even the implied warranty of > > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > > + Lesser General Public License for more details. > > + > > + You should have received a copy of the GNU Lesser General Public > > + License along with the GNU C Library; if not, see > > + . */ > > + > > +#ifndef _BITS_SIGSTACK_H > > +#define _BITS_SIGSTACK_H 1 > > + > > +#if !defined _SIGNAL_H && !defined _SYS_UCONTEXT_H > > +# error "Never include this file directly. Use instead" > > +#endif > > + > > +/* Minimum stack size (5k+256 bytes) for a signal handler. */ > > +#define MINSIGSTKSZ 5376 > > + > > +/* System default stack size. */ > > +#define SIGSTKSZ 16384 > > + > > +#endif /* bits/sigstack.h */ > > -- > > 2.7.4 > > Strictly speaking this is also an ABI change (and what the kernel is > doing is too). If possible I think there should be an effort to get > the riscv folks to rethink this. Aside from being breakage, large > state that has the be saved/restored at context switch time is an > anti-feature. Any reasonable amount of vector state fits in the > existing size. > > If it is to be changed, I suspect 5376 is too small. IIRC other archs > that have large (4k or so?) register files used something like 6k as > the min (1-2k margin for actual execution space). > > Rich Hi Rich I will share this modification in the RISC-V SW mailing list to discuss it. Thank you very much for your suggestions. Vincent