From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: X-Spam-Status: No, score=-3.7 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.6 Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 2B4FF1F47C for ; Wed, 11 Jan 2023 09:29:04 +0000 (UTC) Authentication-Results: dcvr.yhbt.net; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=JQG7nOeF; dkim-atps=neutral Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E954C3850401 for ; Wed, 11 Jan 2023 09:28:59 +0000 (GMT) Received: from mail-yb1-xb30.google.com (mail-yb1-xb30.google.com [IPv6:2607:f8b0:4864:20::b30]) by sourceware.org (Postfix) with ESMTPS id 02128385840F for ; Wed, 11 Jan 2023 09:28:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 02128385840F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-yb1-xb30.google.com with SMTP id l139so14378969ybl.12 for ; Wed, 11 Jan 2023 01:28:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=60qMMO89h4muTLztEtNP/1yuauDlgSOdC37Qf6SptXg=; b=JQG7nOeF63RzFQeP7m2uH9hntY44/3xwtypJrOuvSSLC0FnV5h0qH/Ad9dkP4z7uSk bV+KiqVAFwbfzRKMT9O55erFaL7dJ0ethq0SKNlscljM66BWdUhUV3wBRaOyZNTeYu5D lbuBsSu8sAs7vP2snXtuu4MPHGP3NSX/ov8GXdvcxoivHA4khQWOdEWTOOaEKx4UIucI RBwX7xOw4uHJ6T/ienRYiFlaKul/ahMS5g34/cDedw4IEd6T3d2chlGNcR0p2FQ1o4xa 3ZchBW/8Hvcc3/30v6T+/5mxpRVq0XWtFhwv5rYdib3xMbnIrz/LSVy8av6fvbKzgdZk 1yZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=60qMMO89h4muTLztEtNP/1yuauDlgSOdC37Qf6SptXg=; b=kqUKZS4pvFufia9w8QsYdY+Q4K6fo3HR3XnbjUJwbSPHX7D094KRsoVZ+OyIcEqWZe C3xnshmKHFkndezOENumsPVL/ORDAMXDgOszdQxjnV35RW2/GRYGFPcjh/4KTo4tl9Rd L5IDCO26n6/dtUyZRZLib3CJpPRWP+OVT0vjQls38p10IumBdKByDYrH6qjqMGHWaezF QDQm4nD9b7C1fdGk4mUqyX28QFic8KLthrPB1ydYbRVrucvfVFPuIr+fUtoHhrjViXdO 9DcOEE0fXKPSCe/RBm24RqRs7jfJhrGetZyR+2tb+q3QW7RBGyljP7JUkiQwQ7cXQM3m CiLw== X-Gm-Message-State: AFqh2kqGnFYFvY6Qmu4GJN8tgFdR7sA+ySXRPApuQ69ry1B2N4g2LQA5 Ikf+z6dEfqca5uIwi5FkVnYrFbOU5wAXyCQPojmFBw== X-Google-Smtp-Source: AMrXdXv1ApXxkKay1FDbnD1m8SEcp6U67jOh9F+lgYjIyw+DOzIv5oEtntnlu2MoyYHrJzNbipmekFNpQ/7q0rIU4CA= X-Received: by 2002:a25:392:0:b0:7bb:2f07:448d with SMTP id 140-20020a250392000000b007bb2f07448dmr1503730ybd.32.1673429327336; Wed, 11 Jan 2023 01:28:47 -0800 (PST) MIME-Version: 1.0 References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> <18465ca3-934f-5b3e-170c-1ff0edea3a89@rivosinc.com> <1f8f1d21-4a19-54fe-8b29-bf9e2a8501d7@rivosinc.com> <3a838afe-974b-60bb-a0e5-83e366ec652e@rivosinc.com> <3923eeee-e4dc-0911-40bf-84c34aee962d@linaro.org> <119da65f-e976-f382-3fe1-1585be738352@ventanamicro.com> <8be4d673-f435-429e-9a61-bb49e7820529@linaro.org> <6d13e63f-69b3-6e48-b811-bbfcf3ffb3af@ventanamicro.com> In-Reply-To: From: Andy Chiu Date: Wed, 11 Jan 2023 17:28:36 +0800 Message-ID: Subject: Re: Auto-enabling V unit and/or use of elf attributes (was Re: Adding V-ext regs to signal context w/o expanding kernel struct sigcontext to avoid glibc ABI break) To: Jeff Law Cc: Richard Henderson , Vineet Gupta , Kito Cheng , Philipp Tomsich , Vincent Chen , Florian Weimer , Rich Felker , Andrew Waterman , Palmer Dabbelt , =?UTF-8?Q?Christoph_M=C3=BCllner?= , davidlt@rivosinc.com, Arnd Bergmann , =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= , Szabolcs Nagy , Greentime Hu , Aaron Durbin , Andrew de los Reyes , linux-riscv , GNU C Library Content-Type: text/plain; charset="UTF-8" X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On Wed, Jan 11, 2023 at 2:20 PM Jeff Law wrote: > Fault on first use is well understood and has been implemented on many > architectures through the decades, even with its warts. Unfortunately, we don't have a direct way of acknowledging if an illegal instruction is caused by illegitimate use of V instructions. Unlike ARM64, where reading ESR_EL1.EC is enough to distinguish the fault, we may have to perform a sw decode on the faulting instruction. Then see if it is the first-use fault, or a more general illegal instruction fault. Yes, we may just enable V for a process whenever we find an OP-V major opcode, or a LOAD/STORE-FP with vector-encoded width on illegal instruction. But it could be kind of messy, IF, later extensions would also like to be enabled at first-use-fault. (e.g. ARM has SME followed by SVE). And implementing this decoding logic in sw just seems redundant to me because hw has already done that for us. Besides, ARM64 has individual mappings of traps for the use of FP-related units in EL1 and EL0. So SIMD running in kernel mode would not take additional instruction to enable the unit. I assume these kinds of CSR-controlling instructions would have to flush hw internal buffers to some extent. And doing these takes additional latencies. Andy