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[209.85.210.43]) by smtp.gmail.com with ESMTPSA id w19sm1791869oih.44.2021.11.09.14.18.28 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Nov 2021 14:18:28 -0800 (PST) Received: by mail-ot1-f43.google.com with SMTP id r10-20020a056830080a00b0055c8fd2cebdso899242ots.6 for ; Tue, 09 Nov 2021 14:18:28 -0800 (PST) X-Received: by 2002:a9d:287:: with SMTP id 7mr9061740otl.283.1636496308534; Tue, 09 Nov 2021 14:18:28 -0800 (PST) MIME-Version: 1.0 References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> In-Reply-To: From: Andrew Waterman Date: Tue, 9 Nov 2021 14:18:17 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC patch 0/5] RISC-V: Add vector ISA support To: Andrew Waterman , Vincent Chen , libc-alpha@sourceware.org, Palmer Dabbelt , DJ Delorie Content-Type: text/plain; charset="UTF-8" X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On Tue, Nov 9, 2021 at 2:04 PM Darius Rad wrote: > > On Tue, Nov 09, 2021 at 11:30:49AM -0800, Andrew Waterman wrote: > > On Tue, Nov 9, 2021 at 11:21 AM Darius Rad wrote: > > > > > > On Mon, Sep 13, 2021 at 09:41:13AM +0800, Vincent Chen wrote: > > > > This patchset adds required ports to support RISC-V Vector (RVV) extension. > > > > > > > > Since the length of the vector register in RVV (the theoretical maximum > > > > is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back > > > > up all vector registers in the signal context. This patchset expands the > > > > default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack > > > > size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also > > > > places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the > > > > auxiliary vector to inform user, so user still can know the sutible minimum > > > > signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater > > > > than 128 bytes. > > > > > > > > In addition, according to the specification, the VCSR that combines VXRM and > > > > VXSAT has thread storage duration, so this patchset adds the required user > > > > context operation for it. > > > > > > > > Finally, the RISC-V glibc customized sigcontext.h has been removed in this > > > > patchset. to reduce the synchronization work when new extension support is > > > > introduced to the Linux environment. However, it may bring some backward > > > > incompatible issues. Therefore, I sent an RFC patch > > > > (https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html) > > > > to discuss this modification before this patchset. As I mentioned in the > > > > RFC patch thread, I used OpenEmbeded to evaluate the impact. During the > > > > tests, I didn't get any compiler errors. Therefore, I infer that this > > > > modification may not cause server backward incompatible issues at this > > > > moment. > > > > > > > > 1. The RISC-V V-extension draft v1.0 can be found in > > > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc > > > > 2. The associated kernel implementation can be found in > > > > http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html > > > > 3. QEMU with RISC-V V-extension support can be found in > > > > https://github.com/sifive/qemu/tree/rvv-1.0 > > > > > > > > > > For the record on libc-alpha, I object to these changes. In particular, > > > the lack of a user space API for the corresponding Linux support. More > > > discussion on linux-riscv: > > > > > > https://lists.infradead.org/pipermail/linux-riscv/2021-September/thread.html#8361 > > > > I do not agree with that analysis. The vector extension scales down > > to having potentially very little state (512 bytes on RV64) and we > > expect typical applications-processor implementations to land in the > > 512 - 2048-byte range. This matches AVX, not AMX. Furthermore, we > > want all implementations to take advantage of vectorized C > > string/memory functions without having to explicitly opt in. Not > > doing this would put RISC-V at a significant competitive disadvantage > > vs. other architectures with SIMD units. > > > > The vector extension also scales up to 256 kiB, which, for comparison sake, > is considerably more than AMX. We have good reason to believe that apps/server processors will not get anywhere near an order of magnitude of that limit, and that huge vector regfiles will be the province of HPC. > > There are those that believe AVX should have had some sort of user space > control [1], as well. > > [1] https://lore.kernel.org/lkml/87k0ntazyn.ffs@nanos.tec.linutronix.de/ > > I don't see how having user space control either prevents glibc from using > vector by default when it is available or how it puts RISC-V at a > significant competitive disadvantage. My "competitive advantage" comment was about the need to do the following (quoting from your other message): "A process (or thread) must specifically request the desire to use vector extensions (perhaps with some new arch_prctl() API)" I had assumed you meant that programmers must do this explicitly--which would clearly put RISC-V at a competitive disadvantage. If glibc initialization code makes this API call, then I withdraw my comment. (But then I question the value of the API call vs. the kernel automatically enabling the vector unit, since essentially all processes will invoke the API call anyway.)