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From: "Karumanchi, Sajan via Libc-alpha" <libc-alpha@sourceware.org>
To: Florian Weimer <fweimer@redhat.com>,
	sajan.karumanchi--- via Libc-alpha <libc-alpha@sourceware.org>
Cc: "Mallappa, Premachandra" <Premachandra.Mallappa@amd.com>
Subject: RE: [PATCH] x86: Adding an upper bound for Enhanced REP MOVSB.
Date: Mon, 11 Jan 2021 10:46:16 +0000	[thread overview]
Message-ID: <BN6PR1201MB0081E83C5CB1BDEDE5F6254089AB0@BN6PR1201MB0081.namprd12.prod.outlook.com> (raw)
In-Reply-To: <878s93v84g.fsf@oldenburg2.str.redhat.com>

[AMD Public Use]

Hi Florian,

I have pushed a new patch on top the rebased master branch.

Thanks & Regards,
Sajan K.

-----Original Message-----
From: Florian Weimer <fweimer@redhat.com> 
Sent: Friday, January 8, 2021 7:33 PM
To: sajan.karumanchi--- via Libc-alpha <libc-alpha@sourceware.org>
Cc: carlos@redhat.com; hjl.tools@gmail.com; Karumanchi, Sajan <Sajan.Karumanchi@amd.com>; Mallappa, Premachandra <Premachandra.Mallappa@amd.com>
Subject: Re: [PATCH] x86: Adding an upper bound for Enhanced REP MOVSB.

[CAUTION: External Email]

* sajan karumanchi:

> From: Sajan Karumanchi <sajan.karumanchi@amd.com>
>
> In the process of optimizing memcpy for AMD machines, we have found 
> the vector move operations are outperforming enhanced REP MOVSB for 
> data transfers above the L2 cache size on Zen3 architectures.
> To handle this use case, we are adding an upper bound parameter on 
> enhanced REP MOVSB:'__x86_max_rep_movsb_threshold'.
> As per large-bench results, we are configuring this parameter to the
> L2 cache size for AMD machines and applicable from Zen3 architecture 
> supporting the ERMS feature.
> For architectures other than AMD, it is the computed value of 
> non-temporal threshold parameter.
>
> Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>

Thanks for the patch.  Would you be able to rebase it on top of current master?  There are some non-trivial conflicts, as far as I can see.

Florian
--
Red Hat GmbH, https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fde.redhat.com%2F&amp;data=04%7C01%7Csajan.karumanchi%40amd.com%7C385bb220a2ed40f8383b08d8b3de2881%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637457114064957358%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=o3x1r6WGqvzGwx1Rju%2FEyksBPRJGb%2B3cx9c%2FJHnP%2B3k%3D&amp;reserved=0 , Registered seat: Grasbrunn, Commercial register: Amtsgericht Muenchen, HRB 153243, Managing Directors: Charles Cachera, Brian Klemm, Laurie Krebs, Michael O'Neill

  reply	other threads:[~2021-01-11 10:46 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-07 16:22 [PATCH] x86: Adding an upper bound for Enhanced REP MOVSB sajan.karumanchi--- via Libc-alpha
2021-01-08 14:03 ` Florian Weimer via Libc-alpha
2021-01-11 10:46   ` Karumanchi, Sajan via Libc-alpha [this message]
2021-01-18 17:07     ` Florian Weimer via Libc-alpha
2021-01-18 17:10       ` Adhemerval Zanella via Libc-alpha
2021-01-22 10:18       ` sajan.karumanchi--- via Libc-alpha
2021-02-01 17:05         ` H.J. Lu via Libc-alpha
2022-04-27 23:38           ` Sunil Pandey via Libc-alpha
  -- strict thread matches above, loose matches on Subject: below --
2021-01-11 10:43 sajan.karumanchi--- via Libc-alpha
2021-01-11 17:27 ` H.J. Lu via Libc-alpha
2021-01-12 18:56   ` Karumanchi, Sajan via Libc-alpha
2021-01-12 20:04 [PATCH 1/1] " H.J. Lu via Libc-alpha
2021-01-13 15:18 ` [PATCH] " sajan.karumanchi--- via Libc-alpha
2021-01-13 15:26   ` H.J. Lu via Libc-alpha

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