From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS17314 8.43.84.0/22 X-Spam-Status: No, score=-5.2 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI,NICE_REPLY_A, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id C298B1F8C6 for ; Mon, 13 Sep 2021 19:12:01 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 707E13857426 for ; Mon, 13 Sep 2021 19:12:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 707E13857426 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1631560320; bh=d36Bs9G8zbRJRVASOM2qYJzFkB6wCnPzxAbP4RCAoaU=; h=Subject:To:References:Date:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=kqOWt3G9Ul5xKCQ9CBjfiwhJM2IXKB23t91c9/ZNGa3pky06Nj0AsujZTEtt4miMq 0ypblLRBHf0cqzEznjjuFEt2kze2JddUhDxrekG21HEFfRSGnNaSoHnn9l25R7hP97 p5A0/L25KOy87nq7cWCySOl6Z9IrL5UmPSMTMZeY= Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by sourceware.org (Postfix) with ESMTPS id 230F0385740E for ; Mon, 13 Sep 2021 19:11:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 230F0385740E Received: by mail.kernel.org (Postfix) with ESMTPSA id 21B79610E6; Mon, 13 Sep 2021 19:11:20 +0000 (UTC) Subject: Re: [RFC patch 0/5] RISC-V: Add vector ISA support To: Vincent Chen , libc-alpha@sourceware.org, palmer@dabbelt.com References: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> Message-ID: <4aad9f61-5cef-2a6c-b4f3-9b1dbecf91a0@kernel.org> Date: Mon, 13 Sep 2021 12:11:19 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <1631497278-29829-1-git-send-email-vincent.chen@sifive.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Vineet Gupta via Libc-alpha Reply-To: Vineet Gupta Cc: andrew@sifive.com Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" On 9/12/21 6:41 PM, Vincent Chen wrote: > This patchset adds required ports to support RISC-V Vector (RVV) extension. > > Since the length of the vector register in RVV (the theoretical maximum > is 2^XLEN-1 bits) is variable, a huge and flexible space is needed to back > up all vector registers in the signal context. This patchset expands the > default SIGSTKSZ, MINSIGSTKSZ, and PTHREAD_STACK_MIN to ensure the stack > size is enough for the normal case (VLENB <= 128 bytes). Linux kernel also > places the exact minimum signal stack size in AT_MINSIGSTKSZ entry of the > auxiliary vector to inform user, so user still can know the sutible minimum > signal stack size by sysconf (_SC_MINSIGSTKSZ) if the VLENB is greater > than 128 bytes. > > In addition, according to the specification, the VCSR that combines VXRM and > VXSAT has thread storage duration, so this patchset adds the required user > context operation for it. > > Finally, the RISC-V glibc customized sigcontext.h has been removed in this > patchset. to reduce the synchronization work when new extension support is > introduced to the Linux environment. However, it may bring some backward > incompatible issues. Therefore, I sent an RFC patch > (https://sourceware.org/pipermail/libc-alpha/2020-June/115549.html) > to discuss this modification before this patchset. As I mentioned in the > RFC patch thread, I used OpenEmbeded to evaluate the impact. During the > tests, I didn't get any compiler errors. Therefore, I infer that this > modification may not cause server backward incompatible issues at this > moment. > > 1. The RISC-V V-extension draft v1.0 can be found in > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc > 2. The associated kernel implementation can be found in > http://lists.infradead.org/pipermail/linux-riscv/2021-September/008249.html > 3. QEMU with RISC-V V-extension support can be found in > https://github.com/sifive/qemu/tree/rvv-1.0 What about gcc/binutils: sifive forks for those have quite a few branches with rvv suffix, but it is not obvious which one pertains to the specific version implemented in qemu above. Thx, -Vineet > > Vincent Chen (5): > RISC-V: Remove riscv-specific sigcontext.h > RISC-V: Reserve about 5K space in mcontext_t to support future ISA > expansion. > RISC-V: Save and restore VCSR when doing user context switch > RISC-V: Extend MINSIGSTKSZ and SIGSTKSZ to backup RVV registers > RISC-V: Expand PTHREAD_STACK_MIN to support RVV environment > > sysdeps/riscv/Makefile | 5 +++ > sysdeps/riscv/rtld-global-offsets.sym | 7 ++++ > sysdeps/unix/sysv/linux/riscv/bits/hwcap.h | 31 ++++++++++++++++ > .../unix/sysv/linux/riscv/bits/pthread_stack_min.h | 21 +++++++++++ > sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h | 31 ---------------- > sysdeps/unix/sysv/linux/riscv/bits/sigstack.h | 32 +++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/getcontext.S | 22 +++++++++++- > sysdeps/unix/sysv/linux/riscv/setcontext.S | 22 ++++++++++++ > sysdeps/unix/sysv/linux/riscv/swapcontext.S | 41 ++++++++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/sys/ucontext.h | 2 ++ > .../sysv/linux/riscv/sysconf-pthread_stack_min.h | 39 ++++++++++++++++++++ > sysdeps/unix/sysv/linux/riscv/sysdep.h | 1 + > sysdeps/unix/sysv/linux/riscv/ucontext_i.sym | 6 ++++ > 13 files changed, 228 insertions(+), 32 deletions(-) > create mode 100644 sysdeps/riscv/rtld-global-offsets.sym > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/hwcap.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/pthread_stack_min.h > delete mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigcontext.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/bits/sigstack.h > create mode 100644 sysdeps/unix/sysv/linux/riscv/sysconf-pthread_stack_min.h >