From: "Christoph Müllner" <christoph.muellner@vrull.eu>
To: libc-alpha@sourceware.org,
Adhemerval Zanella <adhemerval.zanella@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Darius Rad <darius@bluespec.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Evan Green <evan@rivosinc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Jeff Law <jeffreyalaw@gmail.com>,
Vineet Gupta <vineetg@rivosinc.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [RFC PATCH 2/3] RISC-V: hwprobe: Add Zawrs test bit
Date: Thu, 18 Apr 2024 11:46:34 +0200 [thread overview]
Message-ID: <20240418094635.3502009-3-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20240418094635.3502009-1-christoph.muellner@vrull.eu>
This patch adds a hwprobe test bit for Zawrs.
The bit position is not settled as the corresponding kernel
patch did not land upstream so far:
https://lore.kernel.org/all/20240315134009.580167-10-ajones@ventanamicro.com/
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
index 4856189f3c..16526c3aec 100644
--- a/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
+++ b/sysdeps/unix/sysv/linux/riscv/sys/hwprobe.h
@@ -79,6 +79,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33)
#define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34)
#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35)
+#define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 36)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
--
2.44.0
next prev parent reply other threads:[~2024-04-18 9:47 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 9:46 [RFC PATCH 0/3] RISC-V: Use WRS.STO for atomic_spin_nop Christoph Müllner
2024-04-18 9:46 ` [RFC PATCH 1/3] RISC-V: Sync hwprobe: Sync extension bits with Linux 6.8 Christoph Müllner
2024-04-18 9:46 ` Christoph Müllner [this message]
2024-04-18 9:46 ` [RFC PATCH 3/3] RISC-V: Implement CPU yielding for busy loops with Zihintpause/Zawrs Christoph Müllner
2024-04-18 17:17 ` Palmer Dabbelt
2024-04-18 20:03 ` Vineet Gupta
2024-04-18 20:25 ` Christoph Müllner
2024-04-18 20:19 ` Christoph Müllner
2024-04-18 20:36 ` Vineet Gupta
2024-04-18 21:10 ` Palmer Dabbelt
2024-04-19 14:09 ` Andrew Jones
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