From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-ASN: AS3215 2.6.0.0/16 X-Spam-Status: No, score=-4.3 required=3.0 tests=AWL,BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 41E2E1F8C6 for ; Tue, 6 Jul 2021 10:52:29 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D7F9382C40C for ; Tue, 6 Jul 2021 10:52:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7D7F9382C40C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1625568748; bh=oV9AZs3XxboeBBsZhy4UiWJDE8Zl4iDX2cL8JTma1ug=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=OuzaA1Z+1aG12KfOmeMqLup23XrJO0EvvR7z0YBpW042/DIpTLha72o5TeOyj26EE HCVJXisfh5JoHddPlWj52ebSB0fiQa8IGa926o8QZPi+KOWL/7UkhdTxHc2wdXl5Xk 6AqJWh4IGNdY61hgiE8DKlVAMb+5f//qZwRp/Vpg= Received: from ozlabs.org (bilbo.ozlabs.org [IPv6:2401:3900:2:1::2]) by sourceware.org (Postfix) with ESMTPS id A5FD33836007 for ; Tue, 6 Jul 2021 10:51:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A5FD33836007 Received: by ozlabs.org (Postfix, from userid 1010) id 4GJzr304Z6z9shx; Tue, 6 Jul 2021 20:51:14 +1000 (AEST) To: tuliom@linux.ibm.com Subject: [PATCH 2/3] powerpc64: Check cacheline size before using optimised memset routines Date: Tue, 6 Jul 2021 20:51:06 +1000 Message-Id: <20210706105107.1866836-2-anton@ozlabs.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210706105107.1866836-1-anton@ozlabs.org> References: <20210706105107.1866836-1-anton@ozlabs.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Anton Blanchard via Libc-alpha Reply-To: Anton Blanchard Cc: libc-alpha@sourceware.org Errors-To: libc-alpha-bounces+e=80x24.org@sourceware.org Sender: "Libc-alpha" A number of optimised memset routines assume the cacheline size is 128B, so we better check before using them. --- sysdeps/powerpc/powerpc64/multiarch/memset.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/sysdeps/powerpc/powerpc64/multiarch/memset.c b/sysdeps/powerpc/powerpc64/multiarch/memset.c index c1aa143f60..056e911699 100644 --- a/sysdeps/powerpc/powerpc64/multiarch/memset.c +++ b/sysdeps/powerpc/powerpc64/multiarch/memset.c @@ -43,16 +43,21 @@ libc_ifunc (__libc_memset, # ifdef __LITTLE_ENDIAN__ (hwcap2 & PPC_FEATURE2_ARCH_3_1 && hwcap2 & PPC_FEATURE2_HAS_ISEL - && hwcap & PPC_FEATURE_HAS_VSX) + && hwcap & PPC_FEATURE_HAS_VSX + && GLRO(dl_cache_line_size) == 128) ? __memset_power10 : # endif - (hwcap2 & PPC_FEATURE2_ARCH_2_07) + (hwcap2 & PPC_FEATURE2_ARCH_2_07 + && GLRO(dl_cache_line_size) == 128) ? __memset_power8 : - (hwcap & PPC_FEATURE_ARCH_2_06) + (hwcap & PPC_FEATURE_ARCH_2_06 + && GLRO(dl_cache_line_size) == 128) ? __memset_power7 : - (hwcap & PPC_FEATURE_ARCH_2_05) + (hwcap & PPC_FEATURE_ARCH_2_05 + && GLRO(dl_cache_line_size) == 128) ? __memset_power6 : - (hwcap & PPC_FEATURE_POWER4) + (hwcap & PPC_FEATURE_POWER4 + && GLRO(dl_cache_line_size) == 128) ? __memset_power4 : __memset_ppc); -- 2.31.1