From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on dcvr.yhbt.net X-Spam-Level: X-Spam-Status: No, score=-4.2 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_PASS,SPF_PASS shortcircuit=no autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id 166CA1F4B4 for ; Wed, 7 Oct 2020 10:06:10 +0000 (UTC) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EEB263857C74; Wed, 7 Oct 2020 10:06:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EEB263857C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1602065168; bh=AaT0/AbafG2LtMWRsZ1LB6ZSF+4OjmpLSOHs1Aj6N78=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=pVq9M7EVSM0qhe1LSxPInPNcntMPCCufHFUeUp80AfwrvxF7WHvmo6z9rYhE40Ill UgskI7TloEVVy9ABXcQNJSnKjiYDc8OZg2hVvlKFtZy1czUmPTObFRe5VXydVDvCcZ OCpgmi446qVkYZ9p0E00DA7jn6mUkuOEggL0XoEg= Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 70DB53857C45 for ; Wed, 7 Oct 2020 10:06:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 70DB53857C45 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00865113E; Wed, 7 Oct 2020 03:06:04 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 032763F71F; Wed, 7 Oct 2020 03:06:01 -0700 (PDT) Date: Wed, 7 Oct 2020 11:05:59 +0100 To: "Bae, Chang Seok" Subject: Re: [RFC PATCH 1/4] x86/signal: Introduce helpers to get the maximum signal frame size Message-ID: <20201007100558.GE6642@arm.com> References: <20200929205746.6763-1-chang.seok.bae@intel.com> <20200929205746.6763-2-chang.seok.bae@intel.com> <20201005134230.GS6642@arm.com> <74ca7e8a61f051eadc895cf8b29e591cc3d0f548.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <74ca7e8a61f051eadc895cf8b29e591cc3d0f548.camel@intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Dave Martin via Libc-alpha Reply-To: Dave Martin Cc: "linux-arch@vger.kernel.org" , "Luck, Tony" , "libc-alpha@sourceware.org" , "Brown, Len" , "Shankar, Ravi V" , "linux-api@vger.kernel.org" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "Hansen, Dave" , "luto@kernel.org" , "tglx@linutronix.de" , "bp@suse.de" , "mingo@kernel.org" Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" On Tue, Oct 06, 2020 at 05:45:24PM +0000, Bae, Chang Seok wrote: > On Mon, 2020-10-05 at 14:42 +0100, Dave Martin wrote: > > On Tue, Sep 29, 2020 at 01:57:43PM -0700, Chang S. Bae wrote: > > > > > > +/* > > > + * The FP state frame contains an XSAVE buffer which must be 64-byte aligned. > > > + * If a signal frame starts at an unaligned address, extra space is required. > > > + * This is the max alignment padding, conservatively. > > > + */ > > > +#define MAX_XSAVE_PADDING 63UL > > > + > > > +/* > > > + * The frame data is composed of the following areas and laid out as: > > > + * > > > + * ------------------------- > > > + * | alignment padding | > > > + * ------------------------- > > > + * | (f)xsave frame | > > > + * ------------------------- > > > + * | fsave header | > > > + * ------------------------- > > > + * | siginfo + ucontext | > > > + * ------------------------- > > > + */ > > > + > > > +/* max_frame_size tells userspace the worst case signal stack size. */ > > > +static unsigned long __ro_after_init max_frame_size; > > > + > > > +void __init init_sigframe_size(void) > > > +{ > > > + /* > > > + * Use the largest of possible structure formats. This might > > > + * slightly oversize the frame for 64-bit apps. > > > + */ > > > + > > > + if (IS_ENABLED(CONFIG_X86_32) || > > > + IS_ENABLED(CONFIG_IA32_EMULATION)) > > > + max_frame_size = max((unsigned long)SIZEOF_sigframe_ia32, > > > + (unsigned long)SIZEOF_rt_sigframe_ia32); > > > + > > > + if (IS_ENABLED(CONFIG_X86_X32_ABI)) > > > + max_frame_size = max(max_frame_size, (unsigned long)SIZEOF_rt_sigframe_x32); > > > + > > > + if (IS_ENABLED(CONFIG_X86_64)) > > > + max_frame_size = max(max_frame_size, (unsigned long)SIZEOF_rt_sigframe); > > > + > > > + max_frame_size += fpu__get_fpstate_sigframe_size() + MAX_XSAVE_PADDING; > > > > For arm64, we round the worst-case padding up by one. > > > > Yeah, I saw that. The ARM code adds the max padding, too: > > signal_minsigstksz = sigframe_size(&user) + > round_up(sizeof(struct frame_record), 16) + > 16; /* max alignment padding */ > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/kernel/signal.c#n973 > > > I can't remember the full rationale for this, but it at least seemed a > > bit weird to report a size that is not a multiple of the alignment. > > > > Because the last state size of XSAVE may not be 64B aligned, the (reported) > sum of xstate size here does not guarantee 64B alignment. > > > I'm can't think of a clear argument as to why it really matters, though. > > We care about the start of XSAVE buffer for the XSAVE instructions, to be > 64B-aligned. Ah, I see. That makes sense. For arm64, there is no additional alignment padding inside the frame, only the padding inserted after the frame to ensure that the base address is 16-byte aligned. However, I wonder whether people will tend to assume that AT_MINSIGSTKSZ is a sensible (if minimal) amount of stack to allocate. Allocating an odd number of bytes, or any amount that isn't a multiple of the architecture's preferred (or mandated) stack alignment probably doesn't make sense. AArch64 has a mandatory stack alignment of 16 bytes; I'm not sure about x86. Cheers ---Dave