From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dcvr.yhbt.net (Postfix) with ESMTPS id BE7901F8C6 for ; Wed, 8 Sep 2021 15:35:00 +0000 (UTC) Received: from localhost ([::1]:50082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mNzbH-0003Qx-GO for normalperson@yhbt.net; Wed, 08 Sep 2021 11:34:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mNzYF-0007su-MJ for bug-gnulib@gnu.org; Wed, 08 Sep 2021 11:31:51 -0400 Received: from mail115-63.sinamail.sina.com.cn ([218.30.115.63]:38999) by eggs.gnu.org with smtp (Exim 4.90_1) (envelope-from ) id 1mNzY8-0000R9-94 for bug-gnulib@gnu.org; Wed, 08 Sep 2021 11:31:50 -0400 Received: from unknown (HELO DESKTOPRITK6E0)([180.111.104.212]) by sina.com (10.69.2.33) with ESMTP id 6138D6020000B561; Wed, 8 Sep 2021 23:26:01 +0800 (CST) X-Sender: youbest@sina.com X-Auth-ID: youbest@sina.com X-SMAIL-MID: 32800551249208 From: =?gb2312?B?y++6o9PC?= To: "'Bruno Haible'" , Subject: Re: [PATCH] stack-direction: Add support for loongarch CPU Date: Wed, 8 Sep 2021 23:25:49 +0800 Message-ID: <022401d7a4c5$d212d0c0$76387240$@sina.com> MIME-Version: 1.0 Content-Type: text/plain; charset="gb2312" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adekxc0Vl9OB/CCpRAG4GxarrtRClg== Content-Language: zh-cn Received-SPF: pass client-ip=218.30.115.63; envelope-from=youbest@sina.com; helo=mail115-63.sinamail.sina.com.cn X-Spam_score_int: 49 X-Spam_score: 4.9 X-Spam_bar: ++++ X-Spam_report: (4.9 / 5.0 requ) CHARSET_FARAWAY_HEADER=3.2, FREEMAIL_FROM=0.001, MIME_CHARSET_FARAWAY=2.45, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: bug-gnulib@gnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Gnulib discussion list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: bug-gnulib-bounces+normalperson=yhbt.net@gnu.org Sender: "bug-gnulib" > -----=D3=CA=BC=FE=D4=AD=BC=FE----- > =B7=A2=BC=FE=C8=CB: Bruno Haible > =B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA9=D4=C24=C8=D5 21:17 > =CA=D5=BC=FE=C8=CB: bug-gnulib@gnu.org > =B3=AD=CB=CD: Sun Haiyong > =D6=F7=CC=E2: Re: [PATCH] stack-direction: Add support for loongarch = CPU >=20 > Hi, >=20 > Sun Haiyong wrote: > > * m4/stack-direction.m4 (SV_STACK_DIRECTION): When the CPU is > loongarch, > > set "sv_cv_stack_direction" to "-1" . >=20 > Thanks for the patch. Do you know a document which explains the ABI of this > architecture (I mean: register usage, max number of arguments passed = in > registers, stack direction, stack alignment, etc.)? >=20 Thanks. > For the moment, I am only able to guess, based on [1] which says that > LoongArch is basically a clone of mips64 with different encoding of = the > instructions. So, I've applied your patch. >=20 > [1] > https://www.phoronix.com/scan.php?page=3Dnews_item&px=3DLoongArch-MIPS > -Copy-Kernel >=20 About LoongArch, see the link: https://lore.kernel.org/linux-arch/20210903095213.797973-2-chenhuacai@loo= ngs on.cn/T/#u >=20 > 2021-09-04 Sun Haiyong (tiny change) >=20 > sigsegv: Improve cross-compilation support for LoongArch CPU. > * m4/stack-direction.m4 (SV_STACK_DIRECTION): Assume the stack > grows > down on LoongArch. >=20 > diff --git a/m4/stack-direction.m4 b/m4/stack-direction.m4 > index 93287254b..e682be97d 100644 > --- a/m4/stack-direction.m4 > +++ b/m4/stack-direction.m4 > @@ -1,4 +1,4 @@ > -# stack-direction.m4 serial 7 > +# stack-direction.m4 serial 8 > dnl Copyright (C) 2002-2021 Free Software Foundation, Inc. > dnl This file is free software, distributed under the terms of the = GNU > dnl General Public License. As a special exception to the GNU = General > @@ -32,6 +32,7 @@ AC_DEFUN([SV_STACK_DIRECTION], > i?86 | x86_64 | \ > i860 | \ > ia64 | \ > + loongarch* | \ > m32r | \ > m68* | \ > m88k | \ >=20 >=20